Hello Team,
I have doubts with the watchdog timer function. The switch startup time will be long and I don't know if it will be able to send rising or falling edges early enough before the watchdog timer time out.
In the datasheet, I read: 'Inputting either a positive or negative logic edge every 610 ms (typical) prevents WDT time out at the /WDO or WDO pin.'
I also read: 'a delay time can be set to between 1.4 ms to 10 s'
So, I understand the maximum delay for an edge on WDI, after the correct level on all voltages, would be around 10,6s.
Did I well understood? Is there a way at the startup (eventually with the adding of components like capacitors) to increase the delay on WDI before an action on WDO?
If no, do you have a similar IC with a watchdog which have a longer time out at startup?
An other point: I read in the datasheet: 'For legacy applications where the watchdog timer time-out causes /RESET1 to assert, connect /WDO to /MR; see Figure 35 for the connections and see Figure 6 and Figure 7 for the timing diagrams.'
As I have no way to make 'a negative pulse to /MR, a SENSE1 voltage less than VITN, or a VDD power down' when /WDO goes low, I imagine this is the way to produce the negative pulse to /MR and to make the TPS386000RGPT restart.
This sentence at the end of the datasheet made me doubt: 'The FPGA does not have a separate watchdog failure input, so a legacy connection is used by connecting WDO to MR.'
Regards,
Renan
