UCC28713: Unstable PSR Controller

Hi Georgios,

Thank you for the query on UCC28713.

Please share the schematic of the flyback circuit to help debug the issue.

Regards,

Harish

Hi Harish, 

Thank you for the answer. 
Here is a schematic of the design. The components crossed out are not populated on the shown test results. 

Thanks a lot for the support, 

Georgios

Hi Georgios,

Thank you for sending the schematic. I think there could be somethings wrong with the signal sensed on the Vs pin, I am still evaluatng the schematic. Can you please confirm the value of transformer inductance and turn ratio used?

Regards,

Harish

Hi Harish, I have checked various values for the Rs1 and Rs2 resistors in fact. 

Turns ratio:

Np[pins 4 - 5]/Ns[pins 7 - 8] = 15:1

Np[pins 4 - 5]/Naux[pins 1 - 2] = 15:1

Np[pins 4 - 5]/Ns2[pins 8 - 9] = 24:1

The primary inductance should be around 3.3mH. 

Hi Georgios,

Considering input voltage 565V, here are my initial observations:

1. The turns ratio of Aux: Sec is 1:1, the Vdd is set to 36V too close to abs max which can be too close.

2. If Rs1 is chosen as 100k, for 36V regulation, Rvs2 should be close to 12.4k

3. Current sense resistor 1.1 ohm seems too low, calculations show for 35W it should be close 2 to 2.2ohms

4. With 20k as in current config, OVP is triggered around 30V as per equation below:

5. The snubber componets especially output diode capacitor could be slightly reduced. I would suggest using standard values for now as shown in the application note below and then tuning once the issue is resolved.

https://www.ti.com/lit/an/sluaac5/sluaac5.pdf?ts=1688635074105&ref_url=https%253A%252F%252Fwww.google.com%252F

Please let me know your observations after making the changes or if you have any questions.

Regards,

Harish

Hi Georgios,

Sorry, there was a mistake in the transformer calculations which I made and a colleague of mine was quick to help. I take back on the points 1,2 and 4 which I told before. Rs1 and Rs2 look fine at 100k and 22.2k as per the turns ratio which have calculated. The ratio of Pri: Sec(36) = 9.23 and NA:Ns (36V) = 0.61, so the Vdd also should regulate to 22V as against what I stated before.

The output capacitor C2 with 33uF seems to be on the lower side. We would recommend increasing it to 300 -470uF and shorting the inductor L1 as the LC ringing might distort winding waveform for good regulation. The IC regulates based on aux winding waveform so Vs pin signal should be clean and not affected by any stray capacitance. The winding with dominant load is going to affect regulation and this will be affected by filtering on each rail, so it would be good to have filtering proportional to the loading of the respective windings.

Please let us know if you have any questions.

Thank you

Regards,

Harish

Thanks a lot for the clarifications and the support. 

I used 1.8Ω for Rs, Rs2 and Rs1 of  22k+120k respectively and I get now a stable 37V with ~1.7Vp-p ripple @ ~11W. I will continue testing and update regarding the status. I haven't changed the output filtering however. What I have noticed so far is that sometimes valley switching is skipped and contorller switches at the peak of the resonance or close to it. Could this issue have to do with the output filtering?

Hi Georgios,

Thank you for the reply. Glad that increasing sense resistor helped with the issue. 

The output filter will definitely have an effect on the regulation and controller behaviour. Shown below are two snapshots of the same circuit with capacitive filter and CLC filter. CLC filter shows a lot of oscillations and unstable behaviour (output voltage shows similar behaviour to what you had posted before). I was not able to capture the results fully because of simulation time. 

Please let us know if you have any further questions.

Regards,

Harish

Hi Harish, thanks for the simulation results. The model in TINA takes a long time to simulate for me, so I also prefer just to test instead. 

I still have not tried with a higher capacitance value at the output, as I still do not have a suitable part number but I noticed the following: 

- Rload = 220Ω: Triggering of fault? OVP/UVLO?? - 36Vrms but large ripple due to OVP

-  Rload = 107Ω: 37.2V and good regulation - Some valleys are skipped

- Rload = 72Ω: 37.2V and good regulation - Most valleys are skipped

- Rload = 54Ω: 35.7V and good regulation - ~80kHz

- Rload = 43Ω: 32.5V and stable regulation - ~80kHz

It seems that I reach a maximum Pout around 24W which if I understand correctly, it comes from the choice of the Rs which is set to 1.8Ω now. Is this correct?

When I set the resistor value @1.1Ω however I do not get stable operation and there is some fault triggering.. 

I am now thinking that it might be that the snubber circuit is causing some fault triggering. What do you think? Should I exchange those parameters too?

Hi Georgios,

I tried calculating the sense resistor again with the specs above, and the value comes close to 1.44 ohms. You might want to change this. and the filter as mentioned above too.

I still feel there could be some noise coupling into Vs pin.

Second, it could be possible the LDO connected rail is preventing loading of the 36V rail causing it to hit CC limit as seen from the data above. Ensure that there is minimum load on the 12V winding.

In CC limit the frequency should start decreasing, but 80khz for both 43 & 54 ohm case nneds to be checked. You might want to practically correlate the power at each point with (1/LI^2*Fsw) and correlate them across the two windings.

 The snubber can be optimized, you can check the app note below for good initial estimate of values and tune further:

https://www.omicron-lab.com/fileadmin/assets/Training_and_Events/Power_Analysis_and_Design-Symposium/2022/Presentation_BirichaDigital.pdf

Let us know if you have further questions based on testing.

Regards,

Harish

Hi Harish, 

Thanks once again for the great tips and support. While waiting for the new components I have tested by changing values and tuned the snubber circuits correctly. 

What I notice now consistently is that when the loading is relatively low <6W @ 36V then the IC trips (OVP? OCP?) My assumption is that the frequency modulation is working well, but not the amplitude modulation region. Do you have any further inputs based on these results?

I would continue testing next week and update the status. 

Thanks for the support.