• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 64 subscribers
  • Views 45 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5069: About Fault Timer

Kaji@PAN
Mastermind 6595 points
Part Number: LM5069

Hello,

Regarding the LM5069-1, I think it latches up when the TIMER pin voltage rises and reaches 4V after an overcurrent occurs, but the delay time does not match the theoretical value.

(Theoretical value)
Capacitance of TIMER pin 3uF ⇒ time to latch-up approx. 140ms
(Actual value: following waveform)
About 80ms

In addition, even if the capacitance of the TIMER pin is changed to 4.7uF, the time until latch-up is about 80ms, which remains unchanged.
Is there any reason why the time lags?

Best regards,

  • 0
    TI__Guru* 91001 points

    Hi Kaji,

    Can you share timer voltage waveform as well.

    Is the device latching off after 80ms or restarting again ?

    Why such long timer period is needed ?

    Best Regards

    Rakesh

  • 0 in reply to Rakesh
    Mastermind 6595 points

    Thank you for your reply.
    I attach two waveforms of the timer voltage.
    CTIMER is 4.7uF.
    The reason why the timer is set long is that the load capacitor has a large capacity and it takes a long time to start up.
    In the abnormal waveform in Fig. 2, the timer ends when the timer voltage is about 1.2V. Latch off after completion.
    The only difference between Figures 1 and 2 is whether the load changed from 7.2A is 9.6A or 10.3A.
    (Question 1)
    What do you think is the reason why the timer voltage ends at around 1.2V?
    (Question 2)
    The red circles in Figure 2 are waveforms that overshoot by about 2ms when the load is changed.
    What could be the reason for this overshoot?
    Is it the effect of constant current control responsiveness?
    Best regards,

  • 0 in reply to Kaji@PAN
    TI__Guru* 91001 points

    Hi Kaji,

    We rarely see customers using timer period more than 10ms because the design would not be able to meet the SOA criteria. If you have large load capacitance, we can manage with dv/dt method 

    Please input your system specifications in design calculator https://www.ti.com/lit/zip/snvu050 and send me for review

    On your test results, the controller might be responding fast in case of larger load steps and discharging the GATE node. Please probe GATE voltage and check.

    Best Regards,

    Rakesh

  • 0 in reply to Rakesh
    Mastermind 6595 points

    Thank you for your reply.
    SOA has already been confirmed and there is no problem.
    So it would help me if you could give me your take on Question 1.
    Best regards,

  • 0 in reply to Kaji@PAN
    TI__Guru* 91001 points

    Hi Kaji,

    Sure.. There could be some limit on the max timer period. To check with the designer, can you please include GATE voltage waveform and share with me.

    Best Regards,

    Rakesh