BQ24780S: Layout recommendation

Ben Huang1

Intellectual 675 points

Part Number: BQ24780S

Sir

We are executing the PCB layout, the brief routing plan is as follows

Top Layer (Placement): IC and other components referring to AGND

Mid1 Layer: AGND and routing

Mid2 layer: PGND

Bottom Layer: (Placement): MOSFETs, Rsense, Inductor, Input and Output capacitors (Intended path for high-current carrying)

For a complete PGND plane, we plan to route PHASE, HIDRV, and LODRV in the mid1 layer

Could you please recommend whether the traces mentioned above is essential to be shielded or not?

Thanks

Regards

Ben

over 1 year ago

0 Jing Zou over 1 year ago

TI__Mastermind 20180 points

Hi Ben,

Phase is essentially the switching node of the buck converter. The high frequency current loop which should be as small as possible. The IC should be placed close to the switching MOSFET’s gate pins and keep the gate drive signal traces short for a clean MOSFET drive. From your layout capture, looks like the switching MOSFETs are placed further away from the IC. To answer your questions, yes, those trace should be shielded.

0 Ben Huang1 over 1 year ago in reply to Jing Zou

Intellectual 675 points

Hi Jing

Thanks for your comment!

The distance between BQ24780S and MOSFET is about 30mm

As understood, GND pouring will introduce additional parasitic capacitance

I have no idea whether the AGND will be quiet as expected due to the parasitic, or actually no need to worry about it.

Regards

Ben

+1 Jing Zou over 1 year ago in reply to Ben Huang1

TI__Mastermind 20180 points

Hi Ben,

The ground current to the power circuit should not go through the small signal circuit ground such that high di/dt noise in the power circuit does not affect the small signal circuit.

For sensing circuit layout, please refer to the app note section 4 in the link below which share the same fundamental concept to all switching chargers.

https://www.ti.com/lit/an/slua808/slua808.pdf?ts=1690306682294&ref_url=https%253A%252F%252Fwww.google.com%252F

Keep the switching node pad, copper or trace between inductor, source of high-side MOSFET, and the drain of the low-side MOSFET as small as possible to reduce the parasitic capacitance between switching node and any other components and to minimize the radiated EMI emission. Also, do not route small signal traces above or underneath the switching node polygon directly.

You can also refer the BQ24780SEVM layout in the user guide linked below.

https://www.ti.com/lit/ug/sluuba6/sluuba6.pdf?ts=1690227754028&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fen-us%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Den-US%2526searchTerm%253DBQ24780SEVM%2Buser%2Bguide%2526nr%253D12

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BQ24780S: Layout recommendation