Hi, team：
Nice to meet you！
Could you help explain the principle of watchdog, and could you help confirm the minimum time of watchdog time? should it be smaller than 0.9s?
Why the time range like 0.9-2.5s？ due to in my customer product, the flash erase time is 1s, could you help check the reset risk during the erasing process?
Hope to get your reply, thanks.
Hi Hailey,
Simply, a watchdog timer is a device that asserts a reset output if it has not received a periodic pulse signal from a processor within a specific time frame.
The Watchdog time out is shows the time frame, and watchdog alerts the system on late faults, and please find the he timing diagram for watchdog
Best Regards,
Sila Atalar
Hi Hailey,
Please find detailed version of the timing diagram below.
WDI pin needs to get a negative or positive edge in the time period of ttout. And the data sheet also provides min and max values for ttout. So basically, If there is no pulse in that time then reset will be asserted.
I'm not sure what is Flash erase time. If the processor won't be able to send a pulse while flash erase happening, since ttout_min is 0.9s , the reset may be asserted. Can you please provide more detail about the requirements? Depending on that, maybe I can suggest another supervisor that suit in your design.
Hope this give more clear understanding for the watchdog aspect.
Best Regards,
Sila Atalar
