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TPS62130A: Simulation problems, review schematics

Part Number: TPS62130A

Hi,

I have a customer using TPS62130A , but why are there small steps in the chip simulation ascending process? 

Please help confirm whether there is any problem with the design.

Please refer to the attached document for simulation diagram and schematic design.

TPS62130A.docx

Many thanks

  • Hi

    It matches the bench behavior, as it is in pulse skip mode. The frequency of pulse is low.

    Shuai

  • Hi Shuai,

    1.When the customer connected the FSW pin to GND, the frequency changed from 1.25MHz to 2.5MHz, and the phenomenon did not improve.

    2. The same circuit input 5V, the output from 1V to 3.3V is no problem (output 3.3V, FSW= high or low are normal), only output 1V or 1.2V, this phenomenon is more serious.

    Could you please help me with how to solve this problem?

  • Hi Rhea!

    Could you pls add more output cap? 2 or 3 22uF. The reason for high output  no problem is that it needs more current to charge the output cap.

    BTW, could you let me what this kind of step impact in customer's application?

    Shuai

  • Hi Shuai,

    Customer feedback output using 2 22uf capacitors output improved, output using 3 22uf capacitors significantly improved.

    Customer demand: Input 5V, output 1V, the current is about 1A.

    The PCB board area of the customer's product is relatively small, and more than 22uf 0603 package capacitors cannot be put down. Is there any other solution without increasing the output capacitance?

    Many thanks~

  • Hi Rhea!

    Firstly, you have not told me why customer can't accept the small step. Actually, it is normal behavior based my side, pls let me know the impact if we don't  improve it.

    Another solution is shrink SS cap.

    Shuai

  • Hi Shuai,

    1. The PCB size of the customer's products is small, and the TPS62130A chip used by the whole board DC-DC cannot be put down if the decoupling capacitor 22uf (0603) is changed to 2 or 3.

    2. The customer's product is in the Layout stage and has not been put on the board yet, so it is not clear how this step will affect the product in the future.

    3. The small SS capacitance value is several hundred pf, which can be significantly improved, but cannot be eliminated, because the FPGA has a clear requirement for the power rise time >0.2ms, and the small SS capacitance value cannot meet the climb time requirement.

    4. For the above reasons, consult the manufacturer whether there is any impact (output capacitor 1 22uf+1 0.1uf), and confirm that this step has no impact on the customer's product, and the customer can accept such use.

    Thanks~

  • Hi Rhea,

    You can check with customer about the below item:

     What loading is the TPS62130A supply for? Between the TPS62130A and the loading, there are whether some filter capacitors?  If so, they maybe reduce the step. Consider the board parasitic and some filter capacitors, recommend customer to test the loading side in fact, maybe there is not or little impact from the loading side.

    Best regards,

    Zhou