We are using TPS7A57 for our design to generate V out =3.3 V@ 5 A from V in = 3.6 V. This V out is given as power input to clock synthesizer for HS ADC. So there is huge constraint on Noise.
Now I'm facing problem with CP_EN pin. As mentioned in datasheet page no 50, TPS7A57 allows the internal charge pump to be disabled for systems that cannot tolerate any switching noise and If CP_EN is connected to GND (CP disabled), the internal circuitry is powered from the BIAS rail. Inorder to use BIAS rail, the device need to be characterized with at least Vbias > Vout + 3.2V. Thus I need to provide VBIAS atleast 6.5V which i can,t generate on my custom board as space constraints are there.
So, I enabled CPEN pin to avoid VBIAS of 6.5 V. Now how much noise is expected on output power rail 3.3 V. Is it safe to give this output voltage to Clock synthesizer for an ADC.
Is there any improvements can I do for my circuit attached below.