TPS62933P: Design verification/validation for FPGA Power circuit

Kshitish Gadre

Part Number: TPS62933P
Other Parts Discussed in Thread: TPS62933

Hi team,

I am currently designing the power circuit for Spartan-7 FPGA. According to the Xilinx Power Estimator, the power consumption for my application is less than 3 W. I have designed a circuit using TPS62933P for the same. I obtained the designs for the individual voltage rails from TI Webench. Could you please verify whether the design is suitable for the FPGA?

Thanks,

Kshitish

6864.Power Supply.pdf

3 months ago

0 Calan Elaya 3 months ago

TI__Intellectual 1355 points

Hello,

Miranda will respond to this soon.

Best,

Calan

0 Miranda Gu 3 months ago in reply to Calan Elaya

TI__Genius 12967 points

Hello Kshitish,

The schematic is overall OK.

I just wonder what kind of Cout you will use? MLCC or electrolytic capacitor? It's hard to find such large 100uF MLCC. MLCC typical values would be 22uF/10uF/..., you may use several 22uF caps in parallel as Cout. Or will you use electrolytic capacitor? Please note the electrolytic cap size is much bigger than MLCC.

0 Kshitish Gadre 3 months ago in reply to Miranda Gu

Prodigy 60 points

Hi Miranda,

I am using an MLCC for Cout and I have already found suitable part numbers on digikey. How would it affect the performance of the converter if I use multiple 22uF caps in parallel, instead of using one 100uF? According to my understanding, adding multiple caps in parallel will reduce the effective ESR which will reduce the output voltage ripple. Are there any other effects/advantages besides that?

0 Miranda Gu 3 months ago in reply to Kshitish Gadre

TI__Genius 12967 points

Hello Kshitish,

I guess your selected 100uF MLCC size could be large, typical 0805/0603 size hardly has such large capacitance.

No big side effects of using MLCC. Our EVM also uses 2x22uF MLCC in parallel.

One thing you should know that MLCC has larger derating with higher DC bias than electrolytic capacitor, below is an example. When you do calculations using Cout value, please consider the effective value instead of rated value.

0 Kshitish Gadre 3 months ago in reply to Miranda Gu

Prodigy 60 points

Hi Miranda,

Yes, the selected MLCC is of size 1210. Also, I will check my calculations again based on the effective value instead of rated value.

Also, one thing I noticed was that the designs that I obtained from TI Webench have a negative gain margin. Shouldn't it be positive to have a stable control loop?

0 Miranda Gu 3 months ago in reply to Kshitish Gadre

TI__Genius 12967 points

Hi Kshitish,

The default generated tps62933 webench circuit, also gets negative gain margin, so I think it's normal.

0 Kshitish Gadre 3 months ago in reply to Miranda Gu

Prodigy 60 points

Hi Miranda,

Yes, although I am trying to understand that how can a system with a negative gain margin be stable. One more thing I noticed is that the y-axis for the phase plot is mapped to Phase + 180. Hence the gain margin is being calculated at 0 instead of -180. Any particular reason for this?