TPS548B22: TPS548B22 related issues

jeno.zhang 

jeno.zhang said:

1. As shown in the following two pictures, the output voltage of BP LDO is written as 2.9V in one place and 5.07 in the other place. Why is it different?

During power-up, BP is initially brought up to 2.9V so that BP can support pin detection.  Once pin detection is complete, the BP voltage is released and rises to 5V, unless it is limited by the LDO drop out and the VDD voltage.  BP is held at 2.9V during this pin detection to allow the pin detection circuitry to have a constant reference voltage even when VDD is only 3V.  BP is allowed to rise to 5V during normal operation to maximize the efficiency of the power conversion by providing 5V gate driver for lower MOSFET Rdson.

jeno.zhang said:

2. What do the following two tables describe?

Table 3 describes the selection of the VSEL to AGND resistor value based on the a 100kΩ BP to VSEL resistor and the desired internal reference (set point for RSP - RSN) to program the output voltage and the desired fault response.

For example, to select a 1.0V reference voltage (RSP - RSN = 1V) and "Latch-off" response on fault, the resistors from BP to VSEL and VSEL to AGND should be 100kΩ and 75kΩ respectively.

A "Latch-Off" fault response indicates that the device will shutdown in response to an under voltage or over voltage fault, and will not attempt to restart the output until the EN pin is asserted low, then asserted high.

The VDETECT_TH Table describes the voltage at each of the pin detection pins (MODE, VSEL, FSEL) when a 100kΩ resistor is connected from the pin to BP, and the described RLOW resistor is connected to AGND while BP = 2.93V for pin detection during start-up.  For example for 100kΩ and 75kΩ the nominal pin voltage is 2.93V x 75kΩ/175kΩ = 1.255V.

Applying 1.255V to the VSEL pin during pin detection, will program the internal reference voltage to 1.00V and the fault response to latch-off.