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UCC2808A-1 - Unregulated PushPull

Other Parts Discussed in Thread: UCC2808A-1, TL431



i will build a unregulated Push-Pull-Converter with the UCC2808A-1.

At fixed 200kHz it should run at nearly 90% Duty-Cycle.


The Current should be limited at nearly 1,2A.

I'm a little bit confused how to set the Current-Limit and what to do with the COMP-Output. At this time i had not found some

App-Note or so, with the necessary information...




  • ARC,

    Since i know nothing about your circuit all i can do is suggest that you review  page 7.  

    COMP is conncted back to the FB pin with a resistor to provide the voltage gain control. More complex feedback may be needed however in this design the poles and zeros for the feedback are provided by the control components around the TL431. (note the COMP on the TL431 is not the COMP on the IC. The one on the TL431 is a test point that should have another name.)

    The current limit signal is filter before feeding into the CS pin and since the pulse width is greater than 50% you can see that there is current compensation added to the current sense signal.   


  • Arc,

    I missed the unregulated part.

    The comp pin can be left open and tie FB to ground.

    The question now is do you want to have any current limit. If so set a current sensing resistor in series with the output switch and provide some high frequency filtering to limit spikes between that curretn sense resistor and the CS pin. 

    The pulse by pulse current limit is between 0.45 volts and 0.55 volts. The design should be such that under maximum load conditions the peak of the current ramp should not get above the 0.45 volts but be aware that it might get to 0.55 volts before it trips. 



  • Thanks for your answer!


    I have build up the circuit and till now its running.

    The current limit i have set how you described.


    For the FB pin i was thinking that i must set there a constant voltage to tie the IC at a constant DutyCycle.

    I had set a voltage divider so that at the FB pin is nearly 0.9V to achive a Duty Cycle of 0.45.

    Is this approach also right or will it also work when i tie FB to ground?




  • Arc,

    There is a DC offset on the current sense lead and a resistor divider between the COMP voltage and the current comparator. The current comparator sets the duty cycle so even if the voltage at the COMP were to be set it would not set the maximum duty cycle as that would be a function of the sensed current.  

    Connecting the FB pin to 0.9 volts will have no effect on the output duty cycle. It sets the COMP voltage high which will also happen if the FB pin is set to ground.

    Your design will generate either a maximum duty cycle because the current signal has not been reached the peak by peak current limit point or something less than a maximum duty cycle if the pulse by pulse current limit has been reached. 

    That is what you get if you have a converter that does not have an active voltage feedback.  According to the data sheet the duty cycle (without current peak detect) will be between 48% and 50% under the test conditions for the IC. Increasing the Ct will decrease teh maximum duty cycle as both outputs are off during the discharge of the Ct capacitor. The recommended maximum Ct is 1 nF and the Rt range is between 10k and 200k.