Dear forum members,
Could you please comment on the following?
Device: TPS3435AFACADDFRQ1
During initialization when the device charges the external capacitance via the internal constant current source what is the maximum voltage that could be present on pins
2 (CWD) and 3 (CRST as a result of the charging process?
The reason for asking is so that we can account for the DC bias effect on the external capacitors.
We are using a 6.8nF COG device for the CWD pin so no de-rating is required due to DC- bias effect but for the CRST capacitor we will be using a 470nF X7R part
where the DC- Bias effect should be considered.
Thank you
