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LP2951: Do not understand behavior when simulating ?

Part Number: LP2951

I'm trying to cut the load with a PMOS FET using the error pin. All my attempts to simulate this result in the output (Vout) of the LP2951 going to 0V. I would expect it to oscillate between on/off. Is it my design and understanding or the simulation model that causes this?

As I read the datasheet the error pin has no behavior influence on the regulator part.

I have tried in both TO PSpice and LTSpice.

  • Hi Thomas,

    The datasheet Pin Configuration and Functions section 5 of the datasheet explains how to connect the pins of the LDO in your schematic. Further details are included in Detailed Description section 7. 

    To use the LP2951 as an adjustable LDO, leave Sense and Vtap pins unconnected (floating).

    Best,

    Eric

  • Those are only connected because the simulator complained about them being unconnected. Connecting them to GND should not matter.
    The problem is when simulating everything works fine until my over current FETs is activated by the Error signal. After that the output of the regulator turns to 0V and stays there. The FETs are supposed to disconnect the load in case the error signal is triggered which is done because of the voltage drop over R1 which forces the regulator to raise the voltage to above it's dropout, or at least this was the idea.

  • Hi Thomas,

    Can you please share the PSpice model so I can also run it on my machine? This may be a limitation with the modeling.

    Can you share the waveforms you see in the simulation?  Does increasing R1 to 17 ohms make a difference? I can't tell if you have drooped by at least 6% of the expected Vout to toggle the ERROR signal or not.

    Thanks,

    Stephen