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TPS7A16: TPS7A1650QDGNRQ1

Manuel CC
Prodigy 30 points
Part Number: TPS7A16


Hi Folks,

I have a question related to the footprint that actually have in my design for the TPS7A1650QDGNRQ1.

In the footprint the central pad for dissipated the heat is like a hatched (see the picture)

In the datasheet recommends a different shape pad, is a complete square pad and not hatch.

I'm Afraid that the pad has not a good o sufficient contact with the expose pad in the chip, and the thermal resistance increase. 

What is the recommendation for the dissipation pad hatch or complete? 

We are having thermal issues with this component; do you think is related to shape pad.

And the solder paste layer is the same hatched.

Thanks for the help.

  • 0
    TI__Mastermind 37155 points

    It's possible that the hatched thermal pad is causing your thermal issues, but we should review your operating conditions first.  What is your Vin, Vout and load current?

    Thanks,

    Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 30 points

    Hi Stephen

    Thanks for your replay .

    The Vin:24V

    VOut:5V

    Iout: 70mA aprox.

    We have vias under the gnd pad, but we afraid this vias are causing solder leakage in the via and increasing the thermal resistance. the Via is 0.3mm diameter.

    Thanks in advance.

  • 0 in reply to Manuel CC
    TI__Mastermind 37155 points

    Hi Manuel,

    Okay so you are dissipating 1.33W across the LDO.  The thermal resistance using the JEDEC spec is 66.2 C/W.  This yields 88C rise above ambient temperature.  If you have a better layout than the JEDEC standard, you will improve on these numbers (for example, our EVM's typically have 25-50% reduction in thermal resistance which would yield 66C rise or 44C rise in this case, respectively).

    We typically use 0.5mm via diameter and 0.25mm hole diameter in our EVM's and we do not see significant solder wicking through the via's.  The exception would be when there are many via's inside the thermal pad, in which case this may be a concern.  The fab and assembly house is required to meet a class 2 solder joint and they may add conductive fill to these vias to prevent excessive solder wicking through the vias inside the thermal pad (see below).

    To assess whether your LDO is exceeding the thermal protection limit, you'll want to add the temperature rise to your maximum ambient temperature.

    There are 2 common solutions to prevent the solder from wicking through a via.  You can also explore either of these solutions to see if they will work for your needs.

    1. Conductive fill in the PCB manufacturing step - thermally this is not as good as bare copper but it's better than nothing.

    2. Via tenting in the PCB manufacturing step - this adds a "tent" over the via which prevents the solder from being able to wick through the via

    Thanks,

    Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 30 points

    Hi Stephen

    Thanks for your response.

    This an image from the footprint looks.

    Picture from the real assembly

    we need to change to a complete pad with better thermal transfer, in this way avoid only four points of contact.

    What do you think is a problem for the vias or the thermal design into the footprint? 

    Thanks in advance.

  • +1 in reply to Manuel CC
    TI__Mastermind 37155 points

    Hi Manuel,

    From these images it certainly looks like your thermal pad vias may not be holding the solder like you suggested, such that the thermal pad may have insufficient connection to the PCB.

    It is correct to say a complete thermal pad would allow better heat transfer.  I would also specify a class 2 solder joint and have your customer work with the fabrication and assembly house to confirm they can meet a class 2 solder joint with this layout and these via's.  If they cannot, then ask about via tenting or conductive fill and see if that will fix the issue.

    Thanks,

    Stephen