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TPSM63602: Thermal Issue for TPSM63602V3RDHR

Part Number: TPSM63602

Hi TI engineers,

I encountered an issue while testing the TPSM63602V3. I observed that one half of the IC exhibits a notable temperature increase, even under no-load conditions. I've attached the schematic, thermal distribution, PCB layout, and photographs to this thread. Could you please take a look at the design and provide your insights or suggestions? Thank you! 

Note: FL1 is a common mode choke, when it is taken out, the 3.3V power supply has no load.

  • Hi Liyang,

    The ground plane on the layout shown above is very small. Properly sized copper area for the ground plane is important to help dissipate heat from the IC. Here is an app note on thermal design and the example layout from the datasheet: https://www.ti.com/lit/an/snva951/snva951.pdf

    Are there other layers of the PCB that you can share?

    Best regards,

    Ridge

  • Hi Ridge,

    Thank you for the suggestions!

    I attached all involved layers here. So the thermal issue is caused by PCB layout? I measured the power loss under no-load condition. It is about 0.5W. Is it normal? Thanks!

    Top layer

    One of inner layers with ground plane

    Bottom layer. The trace on the bottom layer is a connection from FB to Vout

    Best Regards,

    Liyang

  • Hi Liyang,

    Looking at the schematic, the minimum effective Cout looks low. For similar conditions as yours, it is recommended to use a higher Fsw and more output cap at Vout=3.3V. See Table 8-1 of the datasheet for details. Is it possible for you to take an oscilloscope measurement of the SW node? Seeing the SW node behavior will be useful.

    Best regards,

    Ridge

  • Hi Ridge,

    Thank for your support! I gave more output capacitance from 10uF to 60uF. I have not seen the thermal picture yet but I have seen the input current drops significantly! It definitely can work with more output capacitance! Thanks!

    Best Regards,

    Liyang