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TPS7A4501-SP: TPS7A4501-SP Stability Analysis

Part Number: TPS7A4501-SP
Other Parts Discussed in Thread: PSPICE-FOR-TI

Hello,

We are running simulations with the phase and gain analysis of the TPS7A4501-SP, and when we try to simulate the circuit that is in the SEE report, it is inherently unstable with a crossover frequency in the MHz range and a phase <10 degrees. It seems like removing the FF cap (470pF) makes it stable, but we just want to confirm whether or not we are using the correct simulation file, or if there is an issue with the simulation file as we are following the circuit in the SEE report.

Our current simulation parameters are as follows

1. VIN = 15V

2. VOUT = 12V

3. Output capacitance, 22uF, 1uF, 100nF.

4. Input capacitance is 15uF.

5. Feed forward cap 470pF

6. PSpice simulation file: worst case analysis.

We are running the simulation on LTSpice, so Im not sure if that might cause an issue as well.

Thank you

Albert

  • Hi Albert, 

    It seems likely that there is a difference caused by using LTSpice. I can run a sanity check using PSpice and share the results here. 

    Thanks,

    Sarah

  • Albert,

    My simulations using nominal values in PSpice suggest a crossover in the 10's of kHz range is more realistic, but this will be impacted by the actual values of your circuit. Would you be able to share a screenshot of your schematic or at least answer the questions below?

    What is the part # for each output capacitor (or at least the typical ESR of each)? 

    What RTOP and RBOT are you using for your ADJ resistors?

    Thanks,

    Sarah

  • Thanks Sarah!

    I was considering that fact that ESR was having an impact on the performance. I also wondering if the capacitors are not being calculated properly with the capacitors in parallel

    Here are the values

    R1 = 49.9 ohm

    R2 = 34k8

    R3 = 3k97

    C2 = 470pF

    C6 = 1nF

    C7 = 100 nF ESR = 19mohm

    The ESR for the 1nF and 100nF capacitor are from the same family so I used the spec sheet fro the 100nF capacitor https://spicat.kyocera-avx.com/product/mlcc/chartview/300904103104KE

    C8 = 22uF 40V capacitor https://exxelia.com/uploads/PDF/ctc21-ctc21e-v4.pdf with a ESR of 85mohms

    I did try deleting the ESR on the ceramic capacitors, and put the effective ESR on the ceramic capacitor and that seemed to have more of an impact in line to what I would think it would have.

    Currently the Effective resistance, with the current setup, would be 8.5mohm which should be pretty low.

    For reference here is the resulting AC analysis with the effective resistance set at 8.5mohm, and then setting the ESR for each capacitor.

    Effective ESR is 8.5mohm

    ESR set for each capacitor

    Let me know if you get something similar or something with my setup

    Thank you

    Albert

  • Hi Albert,

    Thanks for all of the additional details! It's very helpful for me.

    I would not expect using separate vs equivalent capacitors to make any difference in the results when using basic capacitor+resistor models.

    This is what results look like in PSpice with a load of 1.5A.

    Crossover = 17.69kHz, PM = 92, GM = 21

    I used the Spice models available on the part pages for the ceramic caps you listed.

    The PSpice results seems more realistic for what I would expect for a nominal crossover value as opposed to the results in LTSpice. I'm not certain which components internal to the model would cause such a difference though. If you don't have access to PSpice, then I would recommend you use this model in the free version of the tool (PSpice-for-TI). 

    Thanks,

    Sarah

  • Thank you for the support Sarah! That confirms some of my suspicion with using LTSpice for the simulation. It looked like the transient testing was ok but the AC analysis was behaving strangely.

    I switched over to PSpice for TI and was able to recreate it.

    Thank you

    Albert

  • Happy to help! Thanks for confirming everything is working now on your end.

    All the best,

    Sarah

  • Hi Sarah

    Could you share the PSPICE schematic and setting for me? (I using the PSPICE for TI tooling)

    I want to know the detail about Cout1u and Cout100n component.

    How to impot S2P and setup from the website ?

    Thanks for the sharing

  • Hi Cheney,

    I've already deleted the set of files I was using, but setting up this circuit should still be easy. I don't see this model in the built-in library for PSpice-for-TI yet, so you can download the project files from the part's web page and alter the default schematic to match the screenshot above. I used the default simulation settings for the simulation profile. 

    For the AVX output capacitor models, if you go the capacitor part web pages there is a tab called "EQ Circuit Diagram" (Albert shared a link in their post). This shows the SPICE circuits for the capacitors. I created Hierarchical Blocks for each capacitor in PSpice to simplify the top-level schematic, but the circuit within these blocks is just what is shown on the AVX web pages.

    Thanks,

    Sarah

  • Thanks for the such detail setting.

    This Help me a lot

    Thanks!