Hello, since this module can handle up to 65V on the input, I am concerned about pads 1-4 as the clearances are only ~15.7 mils as shown below:
This is the Ultra Librarian Ecad model downloaded from TI's product page: https://www.ti.com/product/TPSM365R6
If my design will have a 50V input & 3.3V output, I am calculating that you would want a 24 mil clearance between the input pad & EN pad (3 & 2, respectively [EN is directly connected to the input pad in my design]) and the adjacent Pgood pad (1) and 3.3V output pad (4) due to the exposed metal pads (this was calculated using latest revision of IPC-2221B). I took a look at the reference layout in the datasheet and the layout of the TPSM365R6FEVM eval module that utilizes this module and it doesn't appear to account for any special clearances for high input voltages in the layout, see below: 
This is from page 8 of this document. Here, test data is shown on page 13 with an input voltage of 24V and a 5V output (they also have a 3.3V output header selection that I assume was tested). Page 12 shows characteristic curves with the input voltage up to 54V. Was there any special considerations taken during the board production to protect the TPSM365R6 module from high input voltages? Do you suggest any special considerations be taken for the layout with the input voltage set to 50V & the output at 3.3V? Please note the specific part model number I am using is TPSM365R6V3RDNR, which is the fixed 3.3V output module.
Thanks.
