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BQ25798BKUPEVM: Updating of Fault Registers

Part Number: BQ25798BKUPEVM

Dear TI,
I have been able to run the EVM but trying to simulate the hardware faults. The fault registers are not updating although the hardware responds accordingly.
I need help in this matter.
I have one more question: What would be the better ways to simulate the hardware faults and get the exact response in fault registers?
Regards,
Ahmed Ali

  • HI Ahmed,

    The fault flags clear after being read.  The status flags report current status.

    Regards,

    Jeff

  • And what are the steps to simulate the hardware faults? Can you guide about it?

  • Ahmed,

    Can you give me examples of what you mean by hardware faults?

    Regards,

    Jeff

  • How to create over-voltage on VSYS?
    How to create over-current or short-circuit on VSYS?
    How to create over-voltage on VAC1, VAC2, VBAT, and VBUS?
    How to create over-current on IBUS, IBAT, and CONVERTER current?

  • These are the faults I am interested in. I want to create these faults manually so that I can read its status in the respective registers.

  • Ahmed,

    Regarding 1, with the IC power, use a power supply with series diode to apply a voltage higher than the SYS voltage.  The only thing that happens is the converter stops switching until to get above abs max of 20V and then damage.

    Regarding 2, use a small resistance (like 0.1 ohm - 0.01 ohm) SYS to ground close to the IC with short wires.  This one is difficult because if wires are too long or the short happens too quick, the inductive ringing below ground will damage the IC.

    Regarding 3, same as 1 for VBAT.  For VBUS, same concept and the protection mechanism is to turn off the external mux FET.  Applying more than 30V on VACx or VBUS damages the IC.

    Regarding 4, although not listed in the datasheet, each converter switch has cycle by cycle current limit of 7.5A min for Q1 and Q4 and 10A min for Q2 and Q3.   In forward/charge mode there is also IBUS OCP and input current limit (IINDPM).  There is a bit to disable IINDPM.  You can then apply a short duration transient load (to prevent thermal reg from tripping instead unless you want to trip that too) on SYS that will trip IBUS OCP.  Then you can disable IBUS OCP and apply a higher short duration transient load that trips cycle by cycle current limit.  For reverse/OTG mode, there is IBAT (discharge) REG, IBAT OCP and output IOTG (IBUS from VBUS pin) current limit.  There is a bit to disable IBAT OCP, which SLOWLY turns off the external BATFET if tripped, but you cannot disable, only max out, IOTG current limit.  So applying a load on VBUS will likely trip IOTG current limit before anything else.  You could try pulling your load from PMID pin in order to trip cycle by cycle current limit but that isn't a realistic configuration.

    Hope  that helps.

    Regards,

    Jeff  

  • I will do the testing accordingly and will get back to you.
    Thank you for the help. It means a lot.