CSD88599Q5DC: Max FSW

Hello Michael,

Thanks for the inquiry. The CSD88599Q5DC is optimized for motor drive applications and uses the lowest on resistance FETs that could be fit into the package. There are a few reasons why we do not recommend switching at frequencies higher than 50kHz. First, because these are high charge devices, the switching and gate drive losses become dominant at higher frequency and the power dissipation becomes too high. Second, the construction of the packaged device is different from our sync buck power blocks in that the FETs are stacked in the opposite order. In the sync buck device, the sync FET is on the bottom with its source sitting on the thermal pad connected to GND. This provides a good thermal path to GND and low common source inductance. The CSD88599Q5DC has the "control" FET on the bottom with its drain sitting on the thermal pad connected to VIN. The "sync" FET is on top and the path to GND from the "sync" FET is longer with a larger loop area and much higher common source inductance. This becomes a major contributor to switching loss. Ultimately, it becomes a thermal problem and an SOA problem as shown in the datasheet. SOA for the power blocks is different from discrete FETs as explained in the technical article at the link below. I hope this helps. Please contact me via regular email if  you have additional questions.

https://e2e.ti.com/blogs_/b/powerhouse/archive/2019/06/06/choosing-the-right-soa-for-your-design-discrete-fets-vs-power-blocks

Best Regards,

John Wallace

TI FET Applications