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BQ25173-Q1: Questions about BQ25173Q1EVM Q1 and STAT, PG Pins

Naveed Mirza
Prodigy 10 points
Part Number: BQ25173-Q1
Other Parts Discussed in Thread: BQ25173Q1EVM

I have a couple of questions about BQ25173-Q1 charger IC.

  1.  In the evaluation module user guide (BQ25173Q1EVM), I noticed a P-CH MOSFET (Q1) being used; however, in the charger IC (BQ25173-Q1) datasheet, it is not shown. Is Q1 needed in the circuit?
  2. For the STAT and PG pins, an LDO for an external VREF (from an LDO) is being used to visually show the state of the charger’s power good status by enabling the LEDs. Please let me know if the external VREF is required to see the charging status of STAT and PG pins. If not, can the STAT and PG pins be left as floating/no connect by not using an external LDO?

I’ll appreciate your feedback.

Thanks.

Naveed

  • 0
    TI__Guru 72106 points

    Hi Naveed

    Naveed Mirza said:
     In the evaluation module user guide (BQ25173Q1EVM), I noticed a P-CH MOSFET (Q1) being used; however, in the charger IC (BQ25173-Q1) datasheet, it is not shown. Is Q1 needed in the circuit?

    Bill J --  P-CH MOSFET is an optional circuit to reduce current into the voltage divider / FB pin.  With the circuit leakage current will be in 350nA range.   The /PG pin can be used also but will have higher leakage.

    Naveed Mirza said:
    For the STAT and PG pins, an LDO for an external VREF (from an LDO) is being used to visually show the state of the charger’s power good status by enabling the LEDs. Please let me know if the external VREF is required to see the charging status of STAT and PG pins. If not, can the STAT and PG pins be left as floating/no connect by not using an external LDO?

    Bill J -- The STAT and PG pin max voltage is 5.5V.  The LDO provides a 3.3V to power the LEDs over a wide input voltage range.  If your system has a low voltage rail it can be used.

  • 0 in reply to Bill Johns
    Prodigy 10 points

    Hi Bill,

    Thanks for the quick reply. I have follow up questions to make sure we are following recommended guidelines from TI.

    It is now clear from your response that the P-CH MOSFET is being used to reduce the leakage current for the PG pin; however, it is still being pulled up to "Pull-Up" voltage of the LDO in your EVM schematic.

    My question is about not using an external LDO at all. In this case there would be no pull-up voltage present for the STAT and the PG pins. So if we don't use the external LDO, can the STAT and PG pins be left floating or do they need to be terminated/bypassed/connected to the ground?

    We do have a 3.3V rail in our system but we don't want to connect that rail to this circuit for isolation purpose. If an LDO is absolutely needed to pull-up STAT and PG pins, then we will use another 3.3V LDO other that our 3.3V rail we have in our system.

    Please let me know.

    Thanks.

    Naveed

  • 0 in reply to Naveed Mirza
    TI__Guru 72106 points

    Hi Naveed

    Naveed Mirza said:
    My question is about not using an external LDO at all. In this case there would be no pull-up voltage present for the STAT and the PG pins. So if we don't use the external LDO, can the STAT and PG pins be left floating or do they need to be terminated/bypassed/connected to the ground?

    Bill J -- STAT pin and PG pin can be left floating, not used.  Note if used the pull up voltage should be less than 5.5V, max voltage for pins.

  • 0 in reply to Bill Johns
    Prodigy 10 points

    Thanks Bill. Appreciate your feedback!