UCC12040: How to handle the SYNC/SYNC_OK pin when using the internal clock

Hi Steve,

Thank you for your reply. I have an additional question based on your answer, could you please answer it?

Q1
When I researched stitching capacitors, I found that on a certain technical site, they are used with GND1 and VCC2 overlapped.
https://edn.itmedia.co.jp/edn/articles/1706/19/news014_2.html
Is the effect the same as overlapping GNDP and GNDS as recommended by TI? Since it is a common mode, and VCC and GND are in the same phase, can we think that they are the same for the purpose of reducing the current loop?

Q2
10.1 Layout Guidelines in the UCC12040 datasheet states: "To ensure isolation performance between the primary and secondary sides, do not place any PCB traces or copper under the UCC12040 device on the outer copper layer." Is there a problem with overlapping GND1 and VCC2?

Q3.
Since I don't know the insulation performance due to overlap, I am considering the following to satisfy both insulation performance and common mode current loop reduction. Could you give me some advice?
- All layers directly under UCC12040 are prohibited from PCB traces, planes, vias, etc.
- Place the stitching capacitor near UCC12040

Thanks,

Conor

Hi Steve,

Thank you for your reply. 

Steven Mappus1 said:

Designing a stitch cap from VCC to GND would be like placing a physical cap from VCC to GND which is done for the purpose of HF bypass.

I understand that the VCC-GND capacitor plays a bypass role, but does this mean that the high-frequency noise of VCC2 on the secondary side is bypassed to GND1 on the primary side? I thought it would normally be bypassed between VCC1 and GND1 on the primary side, and between VCC2 and GND2 on the secondary side, so I'm concerned that the IC's insulation voltage specifications will drop. Also, is it okay to bypass VCC2 on the secondary side and GND1 on the primary side as long as the application insulation standards are met?

Steven Mappus1 said:

Anytime you route copper beneath the UCC12050, you compromise the isolation voltage rating. Some customers do this because the IC may be rated for 5kV but they only require 2kV but in general it is not recommended to add copper/signal routing beneath the UCC12050, at least on the surface layer. For the inner PCB layers, you will need to consider your isolation requirements against whatever PCB design standards are used.

I understood the following from your comment, is it correct? Please let me know if there are any corrections.

Basically, placing PCB traces or copper directly under the device is prohibited. However, if you can design a board that has a dielectric strength that satisfies the required specifications of the application even with overlap, overlap is an option as a means of mitigating EMI noise.

Thanks,

Conor

Hi Steve,

Thank you for your reply.

Steven Mappus1 said:

please let us know the results and lesson learned?

The stitch capacitor will also report the operation verification results.

Since the UCC12040DVER and AMC1351QDWVRQ1 packages have the same width, we are considering placing them on the front and back sides of the board. This is because the application requires miniaturization. Is there a possibility that placing the above ICs on the front and back sides of the board will be a problem? I would like some advice.

Thanks,

Conor

Hi Steve, 

Thank you for your reply. I would like to clarify the concerns when placing UCC12040DVER and AMC1351QDWVRQ1 front to back. Can front-to-back placement be a problem? If it becomes a problem, what measures should I take?

Thanks,

Conor

Hi Steve,

Thank you for your reply regarding the double-sided arrangement of UCC12040 and AMC1351QDWVRQ1.

In general, it is often prohibited to place components directly under an inductor. Based on your comment, considering the effects of EMI and radiation noise on the UCC12040 (IC with a built-in high-frequency inductor), we are considering not placing any patterns or parts directly under the UCC12040.

However, this custom board is a small, so even if we avoid directly underneath it, there may be some overlap. The custom board width is 16.5mm, while UCC12040 is 10.5mm and AMC1351 is 5.95mm. We verify the radiated and conducted emissions of custom boards, but is there any way to verify them before manufacturing the board? Also I would appreciate it if you could give me any helpful information or advice regarding the above.

Thanks,

Conor

Hi Steve,

Steven Mappus1 said:

Not sure what you mean by "verify them before manufacturing the board"?

I apologize for the unclear explanation.
We are verifying operation with EVM and have not created any custom boards yet. In the future, we plan to implement UCC12040 and AMC1351QDWVRQ1 on both sides to verify the radiated and conducted emissions of the custom board. The intent of the question is to know if there are any points to consider or how to perform simulation before testing with a custom board.

Thanks,

Conor