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LM5023: LM5023 block diagram inquiry

Kang
Prodigy 30 points
Part Number: LM5023

Hello.

My name is Eunseok,

I have a question while looking at the block diagram of LM5023.

I know you're busy, but could you answer a few questions?

1. In soft start operation, there are two n-channel mosfets inside, but isn't the mosfet that receives the EN signal as the gate signal a p-channel?

-->  I understand that the EN signal is always HIGH, but if an N-channel MOSFET is used, the capacitor of the SS pin is not charged.

2. There is an N-channel MOSFET that receives the LEB signal of the CS pin as a gate signal. Is it a P-channel MOSFET?

If the N-channel MOSFET is correct, will the LEB signal be HIGH at the beginning of the LEB and then change to LOW after the LEB delay time?

3. What is the function of the tRESTART block that receives the output of the QR pin's Demagnetizing comparator as input?

 Is it a simple delay role?

I have a lot of questions, so please understand.

Sincerely yours,

Eunseok

  • +1
    TI__Mastermind 23615 points

    Hi Mr. Kang,

    Thank you for reaching out on LM5023. Please find my reply below.

    1. At startup, SS will be low, close to GND. When VCC reaches the start threshold,  an internal current source will charge the external SS cap, so SS will ramp linearly. COMP will be clamped close to the SS level, so it will also rise linearly. SS voltage rises at start-up and should not interfere during normal during normal operation. Any fault like an OVP detection at QR, or VCC undervoltage, or the overload detection timer will pull SS down internally. So, it should be pmos.. But will have to confirm.

    2. Yes you are correct LEB will be high during the blanking interval time.

    3. The tRESTART block is used to allow the IC to start switching if the QR signal stays low for longer than the Trestart time (~12 us). This situation can occur when the device is first powering up and when waking up from sleep mode (COMP > 120mV + hysteresis). It is not stated in the datasheet, but the tRESTART block delivers a short pulse (about 50 ns wide) to the AND gate every time the QR input signal crosses below 350mV Demag comparator threshold. It is not a continuous High level. Usually the first zero crossing at QR will generate the pulse that will set the OUT flip-flop high. But at start-up and wake-up, there are no zero-crossings, only a 0-V level at QR. So if this state persists for longer than ~12 us, the tRESTART block automatically sets its block output High continuously to allow the PWM comparator to trigger the OUT flip-flop.

    Regards,

    Harish