TPS7B68-Q1: Thermal Resistance Condition

Yuya Shoji

Part Number: TPS7B68-Q1

Hi team,

I got customer inquiry and I'm BCCing this thread to the customer.

Per 6.4 in D/S, could you tell me the specific condition when here values are spec'ed? In particular, the customer would like to know following:

if this was simulated with 1s or 2s2p
layout information with area value (xx mm^2) in each layer

Best Regards,

Shoji

10 months ago

+1 Nick Butts 10 months ago

TI__Mastermind 43605 points

Hey Shoji,

The datasheet thermal metrics are simulated using the JEDEC High-k board layout specified in JESD51-7. The High-k board is a 2s2p board. As this document is not publicly available for free, I will send you more specifications for this board offline.

Regards,

Nick

0 Yuya Shoji 10 months ago in reply to Nick Butts

TI__Expert 3430 points

Hi Butts,

I got the data. Thank you for the info.

Out of curiosity, are our LDOs simulated with JEDEC High-K board?

Best Regards,

Shoji

+1 Nick Butts 10 months ago in reply to Yuya Shoji

TI__Mastermind 43605 points

Hi Shoji,

Yes that is correct.

Regards,

Nick

0 Yuya Shoji 10 months ago in reply to Nick Butts

TI__Expert 3430 points

Hi Butts,

I SEE. This info is super helpful!

Best regards,

Shoji

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TPS7B68-Q1: Thermal Resistance Condition