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UCC12050: UCC12050DVE Negative rail

Part Number: UCC12050
Other Parts Discussed in Thread: UCC12040

Hi all

I want to create positive and negative rails using two UCC12050DVE

Is this possible to treat them as any other isolated psu? whereby connecting one normally (GNDS to isolated GND.) and the other VISO to the GNDS of the other ? Making GNDS on one supply the negative output voltage?

  • as per image for the negative rail...

  • Scott,

    Each UCC12050 can be treated as independent isolated output voltage rails similar to independent windings of a transformer. The outputs can be referenced to floating nodes other than GND or inverted to produce -5V as you've proposed. Thanks for connecting through E2E.

    Regards,

    Steve

  • Perfect .. I will proceed!

    one other question. The EVK uses overlapped layer 2 and layer 3… to create a decoupling capacitance…

    does that not affect the reinforced isolation as per iec61010 clearances ?

    you are very strict about the 8.1mm clearance on layers 1 and 4 (top and bottom copper)

    it’s not totally clear to me which clearances in iec61010 apply to the inner layers of the PCB ? 

  • Scott,

    You have the basics down in that surface layers (air) have different spacing requirements compared to internal PCB layers. Some designers prefer not to introduce anything into the design that might compromise the isolation barrier and other customer like the use of PCB stitch caps and/or the addition of a physical HV leaded Y-capacitor across the isolation barrier. It really depends on how much EMI mitigation is needed based on what other HF signals might be present in the system, and how much isolation is required. Check out this E2E post here.

    Also, I took a look at IEC 61010 and see that for parallel interior conductors on different layers (stitch cap), insulation thickness needs to be 0.4mm. The stitch cap construction is best described by "C" in the below diagram from IEC 61010.

    Regards,

    Steve

  • I must say, the responses to these question have been magnificent... Thank you

    I can tell you now that your competitors do not answer like this Slight smile

    I like the idea of a stitch cap using internal layers, ive just only ever used actual Y-Caps before.

    I am targeting 600Vrms CATII reinforced insulation here... Does the above only apply to voltages <=300Vrms?

    0.4mm internal insulation won't comprimise the 600Vrms reinforced isolation, right?

    As my target voltage for isolation is 600Vrms CATII minimum, i am looking at IEC61010-2-033 (as this will be a handheld product)

    Section K.101.4.3 states;

    If we look at K.103

    I can't find any reference to CATII in the 61010-2-033 tables, so perhaps i just need to confiorm with the pcb house that the insulator between the layers meets 9600V (which would actually give me CATIII rating) dielectric strength for my given layer-layer spacing?

  • Scott,

    I have experience with PCB and power converter design and am able to help with design decisions that optimize performance of TI PMICs. However, the specific decisions made around isolation spacing need to come from you. Different applications have different key concerns driving their PCB design decisions. You seem to be targeting IEC guidelines but other customers are following IPC and even JEDEC standards which are more applicable to PCB design.

    A PCB stitch cap is nothing more than a parallel plate capacitor. You can see from the UCC12050EVM-052, that it takes a significant amount of conductive area to produce only 11pF of capacitance but it has a huge impact for mitigating CM EMI if your design can allow it? One way to build confidence might be to order the UCC12050EVM-052 and some spare UCC12040 IC samples to maybe run some Hipot isolation tests, if you have HV test equipment available?

    Thanks for the compliment on the support you're receiving and for your consideration of TI PMIC products. E2E is one way, TI strives to provide world-class Applications customer support.

    Regards,

    Steve