• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 62 subscribers
  • Views 97 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC21320-Q1: VDDx UVLO: If VDDA is below UVLO, but VDDB is OK, do only OUTA will be held low while OUTB continiouly follow the input signal?

Yoshiki Ochi
Expert 8245 points
Part Number: UCC21320-Q1
Other Parts Discussed in Thread: UCC21551

Hi team, 

If VDDA is below UVLO, but VDDB is OK, will only OUTA be held low while OUTB continiouly follow the input signal (and vise versa)?

Regards,
Ochi

  • 0
    TI__Expert 5190 points

    Hello Ochi-san, 

    Yes, your understanding is correct. This situation happens more often if customer is using bootstrap topology, since the bootstrap capacitor takes time to charge up. 

    Our UCC21551 series behaves better in this type of scenario since the UVLO ON delay time is now 10us max, compared to 100us max in the UCC21320 series. Therefore, it would take less time from the power supply going above UVLO to the device start outputting PWM. Check it out and let me know if you have any additional question! 

    Thanks, 

    Vivian