UCC28513: CLK2 timing and synchronizing to external clock

Hello Erick, 

Thank you for your questions about the UCC28512 Combination PFC/PWM controller. 

I'll answer your question in reverse order: 

Yes, App-note SLUA296A shows a recommended way to synchronize UCC28513 to an external clock, using a CMOS quad NAND-gate device (CD4011).  This is an old application note, still valid, but other devices besides the CD4011 may be used to generate the sync pulses and RT adjustment voltage, provided that the revised circuit follows the same operating principles of the SLUA296A circuit.   

CLK2 (and CLK1) is an internal narrow pulse generated by an oscillator circuit (not shown in the block diagram) that conforms to the timing relationship of the oscillator sawtooth waveform shown at the top-left corner of the Block Diagram.  CLK2 can be seen to correspond roughly to the discharge time of the sawtooth waveform, however the equation for RT shown in the Detailed Pin Description for the RT (pin 2) (on page 10) suggests that CLK2 (and probably CLK1) has a fixed pulse width of about 200ns.   
The factor of 2.0 x 10^-7 subtracted from the normalized switching period (1/fS) would account for a minimum PWM off-time at GT2. 

CLK2 discharges the internal timing capacitor CT whose value is unknown because internal current mirrors are probably adjusting the IRT current to a lower value to allow for very small capacitance.  But, the same RT equation on page 10 indicates that CT may be considered to have an effective value of ~31pF to result in an oscillator frequency based on one time constant.  In reality 31pF is rather large for an IC, and CT's true value is likely to be much smaller.  Fortunately, it is not really necessary to know its true value to understand how the timing functions.   

Regards,
Ulrich

Hello Erick, 

The period of CLK2 is the same as as the oscillator period set by RT.  This period is the inverse of the switching frequency fS that is chosen by the designer before calculating the value of RT to obtain that frequency.  The RT equation is on page 10, as I mentioned earlier. 

RT sets a charging current which charges the internal CT up to an internal threshold.  Once the oscillator ramp (CT voltage) reaches that threshold (to generate a 4-V sawtooth waveform at CT_BUF), the CLK2 pulse is generated to discharge CT and start the ramp again.  

Regards,
Ulrich

Hello Erick, 

As specified in the datasheet, yes, the effective threshold voltage is 5V (typ) and based on a 4-V ramp, the OSC min voltage would then be 1V (typ). 

As written in the "Detailed Pin Descriptions" for RT (Pin 2) (page 10), the voltage on RT is 3V.  

Regards,
Ulrich