TPS7H1101-SP: Gain and Phase Margin Help

Hi Joseph,

What is the ESR of the caps you are testing with? Is this a simulation or results measured on the bench?

This device does not require large output capacitances to achieve stability.

Thanks,

Sarah

Hi Sarah,  ESR is 19.3mΩ which is divided by however many I have in parallel.

It's a simulation not bench.

Thanks Joseph,

When I recreate your operating conditions, but use the capacitance from the default model, I see a phase margin of 61 deg. This is in line with what we would expect from the device using more reasonable COUT values. 

When using your capacitors (but decreasing the 330u to only 1 cap instead of 12), I still see a PM of 48 deg. Is your analysis of tolerances where it shows PM<30deg? 

Regardless, crossover is much lower than the results from the default schematic capacitor sim run due to the placement of the ESR zero. Lowering the total output capacitance, such as in the default schematic, would help with this.

Thanks,

Sarah

Sarah yeah I'm doing a Monte Carlo using the tolerances you see in my schematic.  Uniform Distribution cause Gausian looks real bad.  500 runs.  In order to stay above 30deg I need 12 of the 330uF caps.  Also note that the cap in parallel with Rbottom does help a bit.  I'm thinking of violating our 30deg requirement and specifying that the part is not capable given the requirement we have for such large tolerances on the output caps etc.

Thanks for confirming Joseph. Can you clarify where the ~90% tolerance of the ESR comes from? That is the key driver of variance in your results, not the device itself.

It would probably also be more realistic to place each capacitor (and parasitic ESL/ESR) individually on the schematic instead of lumping together when running tolerance simulations so that the simulator can randomly vary them separately instead of assuming each of the 12x 330uF caps (for example) all take the exact same amount of variation.

When I perform 500 simulations with uniform distribution and separate COUT caps with the tolerances you're using, the lowest PM I observe is 39deg. Given that this is Uniform instead of Gaussian, I would also expect this result to be more pessimistic than the majority of cases. 

Thanks,

Sarah

Sounds like the only delta may be the PSpice model.  Are you using this one.....

* TPS7H1101A-SP Worst Case Analysis (WCA) Model
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* (C) Copyright 2021 Texas Instruments Incorporated. All rights reserved.
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** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer.
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* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
* Released by: Texas Instruments Inc.
* Part: TPS7H1101A-SP
* Date: 17NOV2021
* Model Type: Worst Case Analysis
* Simulator: PSpice
* Simulator Version: 17.4.0
* EVM Order Number: TPS7H1101SPEVM
* EVM User's Guide: SLVU944B – REVISED OCTOBER 2020
* Data sheet: SLVSDW6C – REVISED APRIL 2021
* Model User Guide: SLVUBT7A - REVISED APRIL 2021
*
* Model Version: Rev C
*
*****************************************************************************
*
* Updates:
*
* Final 1.00
* Release to Web
*
* Rev A/B - April 2021
* 1. Changed file to Windows CRLF instead of Unix LF and added TPS7H1101A-SP_WCA
* subcircuit name to the .ENDS statement to avoid potential error messages related
* to the .ENDS statement
* 2. Added missing TI header to the lib file
* 3. Updated device subcircuit name to "TPS7H1101A-SP_WCA" instead of "TPS7H1101A-SP"
* 4. Updated device subcircuit pin order to make the part symbol more convenient
* 5. Updated model to use GND pin instead of directly connecting to 0V node where it
* is relevent to do so
*
* Rev C
* Temporary re-release of original revision.
*

Sarah can you also send some screen shots of your simulation settings?

The tolerance on the ESR is the requirement for my program unfortunately.  I do want to try and get it relaxed but sounds like I may not need to if your sim (which is the "same" as mine) is passing.

Also, I re-ran the sim after separating out the passives (vs lumping them on a single symbol) and didn't seem to make much difference in my sim..  Did you notice if it made a difference in yours?

Hi Joesph,

I will attach my archived project files so you can see exactly what I see. I have been using the same simulation settings throughout our correspondence. 

tps7h1101a-sp_wca-2024-01-25.zip

I decided to take a look at which extreme end of ESR values was leading to the minimum phase margin case. It appears that sim runs with the lowest ESR were resulting in the lowest phase margin. One potential work around to for your ESR tolerancing requirements could be to simply add some series resistance. Would this be a viable solution for you? 

I have this approach currently set as the default schematic and sim profile if you want to take a quick look at the results yourself. 

Thanks,

Sarah