Hello, i have severals questions regarding the LM5069 Reference designs and the Design calculator:
My design uses LM5069 to limit current to approx. 20A @48V and to protect against short circuit. Hot-plug scenarios are not relevant here . Reverse voltage protection is realized by a 100V-Diode to GND. We also have high output capacitances of several mF, so the external dv/dt circuit is required.
dv/dc curcuit:
- Refering to the Design-calculator, there is a minimum recommended slew-rate value for Cdv/dt. As we have high capacitances of several mF, in my design im currently using 120nF which results in several 100ms slope time and is almost the minimum recommended slew-rate . Is there a reason not to reduce slew-rate any further or is there a fixed lower limit for the dv/dt slope? Im asking this because i would like to reduce dv/dt even further to compensate for dv/dt capacitor tolerances.
- Can the dv/dt circuit somehow affect the current regulator behaviour in a fault event in a negative way?
- Just as a Remark: It should be noted in the Datasheet or Calculation-Tool, that for Cdv/dt, DC-Bias should be considered for Class2 MLCC which most likely would be used in first design approaches.
Shunt Resistor:
- We want to set the current limit to a specific value which leads to a non-integer shunt-resistor value. In this application it is 3,2mOhm. The application note recommends using an additional resistor-divider in parallel to the Shunt resistor. I still would prefer to use two shunt resistors in series (3mOhm+0,2mOhm) instead but have some doubts if the shunt solder joint resistance may have a negative impact on that. Do you have any experience with this approach? Which one would you prefer?
- When using the TI-design tool for dimensioning the external resistor divider, does it include tolerances of the two additional resistances (1%) ?
Thank you!
