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[FAQ] TPS6594-Q1: How do I enable EN_DRV?

Part Number: TPS6594-Q1

Introduction

This FAQ will cover enabling the EN_DRV and the preliminaries needed for it.

Since this FAQ covers both TPS6594/TPS6593 and their variants, there will be slight differences on the implementations. The only way to enable EN_DRV is through the communication interface using either SPI/I2C. The Watchdog and ESM need to be configured and running or disabled along with any interrupts cleared in order to write the enable bit for EN_DRV.

I2C commands as follows: [Base address]: [Write/Read], [Register address], [Write_Data:Mask]

SPI commands as follows: [Base address/Page#]: [Write/Read], [Register address], [Write_Data:Mask]

See the end of the post on example usage

Assumptions: The PMIC(s) has successfully powered up, REGISTER_LOCK is not enabled, the nRSTOUT pin has released (signifying that the PMIC is in known good state), and being the in ACTIVE state.

Implementation

At the moment the nRSTOUT pin is released into the ACTIVE state, the interrupts need to be negotiated

  1. Go into the ACTIVE state
  2. Configure the ESM & WD
    1. WD
      1. Configure & perform: B or C
      2. Disable the Watchdog
      3. Enable the Watchdog and exit the Longwindow into WIN1 & WIN2
    2.  ESM
      1. Configure & perform: B or C
      2. Disable the ESM
      3. Enable the ESM and apply the signal to start
  1. Negotiate all interrupts form registers 0x5A to 0x6C on Page0
    1. Including the WD interrupts should there be any
  2. Write the enable EN_DRV high
    1. 0x48: Write 0x80 0x01:0xFE
    2. 0x48/00: Write 0x820 0x01:0xFE

 

I2C & SPI command Write Mask

[Write_Data:Mask]: If we wanted only to write certain fields to the register from the Write_Data we apply the Mask.

The mask allows any 0s in a byte pattern to go through and write to the current register without destroying the previous bit pattern in the register.

Ex. Writes 3 bits to the register pattern

  1. Current Register value: 0b1101_0011 [0xD3]
  2. Write data: 0b0011_1001 [0x39], Mask: 0b1100_0111 [0xC7]
  3. Register after Write: 0b1111_1011 [0xFB]

Considerations

  • The WD base address is 0x12 and can either be on
    • I2C1 bus
      • If either GPIO1 or GPIO2 is configured to anything, but I2C2 bus functionality
    • I2C2 bus
      • GPIO1 and GPIO2 is configured to I2C2 bus
    • There are some part numbers that have a Disable Watchdog pin, this does not disable the WD EN bit. It instead sets the WD_PWRHOLD which causes the WD to continue to be enabled, but continue to stay in the Longwindow. The device will not be able to set EN_DRV in the Longwindow
    • In a multiple PMIC system, the primary PMIC will typically be handling this, but the secondaries can do this as well, but the same state settings apply (In ACTIVE state & no interruptions)
    • Refer to the devices User’s Guides and Datasheets for base address and Watchdog address as these differ from Part Number to Part Number