TPS546C23: Multiple PMBUs Communication

Sujith Mohandas said:

 1)Could you please explain to me how this device TPS546C23 is tolerant of clock stretching by another device on the same bus?

Several things allow the TPS546C23 to be tolerant of clock stretching by another device.

1) Clock stretching extends the CLK low period, delaying the rising edge of CLK.  It does not add additional edges to CLK.

2) The TPS546C23 does not have an internal clock synchronized to the incoming CLK, it responds only to the falling and rising edges of the incoming CLK.  As long as the CLK low period is greater than 300ns and no more than 25ms and the clock high period is at least 300ns, the CLK need not be constant.

3) When a PMBus transaction targets a different address than the one used by the TPS546C23, it ignores all data on the bus until the next START event (falling DAT while CLK is high).

4) The TPS546x24y family of devices only clock stretches during specific bits within data bytes when transactions are addressed to its device address.

Sujith Mohandas said:

2)) Does clock stretching supported device TPS546A24A  will interrupt the functionality of TPS546C23 ?

No.  The TPS546x24y family of devices will not interfere with the operation of the TPS546C23 device on a shared PMBus physical layer.  This has been done many many times with other customers.

Sujith Mohandas said:

3)Is there any issue if we tie all PMIC ALERT pin ?

It is common that all ALERT pins are connected together and the ALERT is pulled low when any device wants to issue an ALERT.  SMBus uses the Alert Response Address (ARA) to allow the system to identify which device is asserting ALERT.  A device which supports ARA, including both the TPS546C23 and TPS546A24A, asserting ALERT will respond to a transaction starting with the Alert Response Address + Read Bit with it's device address, and will then release the ALERT.  This allows the system identify the device generating the ALERT to follow up by reading STATUS_BYTE or STATUS_WORD.

Standard bit arbitration will cause the device with the lowest Target Address to win a contested bus if multiple devices are asserting alert.  After successfully responding with it's address, a device should released it's ALERT so the system can know if it needs to poll ARA again for more alerting device addresses, or begin reading STATUS information.

Sujith Mohandas said:

I want to make sure that my PMBus architecture is proper ? Please see below image

Your graphic has CLK and DAT of Device 2 - TPS546A24A swapped.

All three devices should have their DAT pins connected to the same net

All three devices should have their CLK pins connected to the same net

Both devices should have their ALERT pins connected to an interrupt digital input of the Raspberry Pi Microcontroller.

Also, I would not recommend using address 0x02 for the TPS546C23, this is a reserved address for CBUS per the I2C specification, and the TPS546A24A can not be pin programmed to address 0x03.  In order to avoid reserved addresses, and select an address which can be programmed by both devices, I would recommend using addresses 0x12 for the TPS546C23 and 0x13 for the TPS546A24A.