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TPS65219: TPS65219 without output

Part Number: TPS65219

Hi,

Here is the TPS6521907 Schematic, and the startup waveforms.3.3V is the first PMIC rail. Does it caused by the FSD? But it seems different Powering the AM62x with the TPS65219 PMIC (Rev. B) (ti.com)

  • Hi,

    Thanks for reaching out. We need clear information to understand the issue. Could you share the schematic in a searchable PDF?

    Could you also identify the signals in the scope capture and specify the time scale used?

    Thanks,

    Brenda

  • Hi 

    Sorry, it's a little difficult for Customer to provide the schematic PDF, but I will try as much as I can. 

    The signals in both of the captures: Yellow->PS5V(5V input), Green->EN (5V), Red->DCDC2(3.3V output). time scale: First capture 2ms/div, Second capture 50ms/div.

  • Thanks for identifying the signals in the scope capture. Here is my feedback while you get the full PMIC schematic:

    • TPS6521907 has LDO1 configured as "bypass". The output of this rail is set by the VSEL_SD pin with the following polarity:
      • VSEL_SD High: LDO1=3.3V (behaves as bypass and requires 3.3V at PVIN_VIN)
      • VSEL_SD Low: LDO1=1.8V (behaves as a fixed 1.8V LDO)

    • LDO1 cannot be supplied by a LDO3 or LDO2 because those rails are assigned to the same slot in the power-up sequence. This means LDO1, LDO2 and LDO3 are turned-ON at the same time and one cannot be used to supply the other.

    • If customer needs 1.8V on LDO1, I would recommend having a pull-down resistor on VSEL_SD and supplying PVIN_LDO1 with Buck2 (V3.3VM) or VSYS (PS5V). 

    Thanks,

    Brenda

  • Hi Brenda,

    The VSEL_SD is controlled by MCU and setting as High to config LDO1 as Bypass mode (for verifying, they also tried pull-up resistor, but result is same), so in this case, the input 1.8V (V1.8VM) of LDO1 can be from the output of LDO3 (V1.8VM).

    For the register setting, they all used the default values, didn't make any changes on the registers.

  • Hi,

    The VSEL_SD pin must have a pull-down resistor to GND and not a pull-up if customer wants 1.8V at the output of LDO1. Additionally, PVIN_LDO1 must be supplied with Buck2 (V3.3VM) or VSYS (PS5V).

    Thanks,

    Brenda

  • Hi Brenda,

    We have done what you suggested, but it still has the issue. 

    For the first power on, what are the values in registers? I see that the default values are from NVM, but what is the exact value? 

    What conditions can cause the three pulses on the power rail?

  • Hi,

    What output voltage did you get on LDO1 when the changes were made on PVIN_LDO1 and VSEL_SD? Have you get the searchable schematic in PDF so we can help with the review?

    The default NVM configuration for TPS6521907 is described in the following document: www.ti.com/.../slvucl9

    Thanks,

    Brenda

  • Hi Brenda,

    Thanks for your support.