This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] TPS28225: What are the design considerations for the TPS28225’s 3-State PWM Input?

Part Number: TPS28225

3-State Input with Single Pin Controller

The TPS28225 has a 3-state input that allows the controller to use a single pin to drive two output FETs as well as set both outputs low by setting the PWM pin to high impedance in the 3-state window. To use only one input from the controller for PWM, the EN/PG pin must be connected to VDD and the controller must be able to set the PWM pin to high, low or high impedance. Figure 1 shows an example implementation of a single output controller with an optional RC filter on the PWM signal as well as an optional pulldown resistor on the PWM signal.

Figure 1 – TPS28225 3-State Single Input Example Schematic

Disabling 3-State Input Mode

If the 3-state mode is not needed, a pulldown resistor (R1) that is external of the driver can be utilized to disable this operation. By setting R1 to 3.5kohm or smaller, the pulldown network will now set the PWM pin to low if PWM is left floating. Adding a resistor of value greater than 40kohm will ensure the floating PWM pin is high impedance and allow for 3-state operation, but R1 is not required. A pulldown resistor of value between 3.5kohm and 40kohm will cause unintended operation of the 3-state circuit and should be avoided. The PWM pin has an internal pullup resistor of 27kohm to VDD and a pulldown resistor of 13kohm to ground. This internal resistor divider network is designed to pull the PWM signal into the 3-state window if PWM is left floating.

PWM Signal Considerations

To ensure proper steady-state operation, the PWM signal to the gate driver should follow these guidelines:

  • Input pulse width of at least 30ns
  • A clean, low-noise square wave with slew rates on the rising and falling edge that are significantly faster than the 250ns hold-off timer
  • Adequate PWM voltage levels to avoid the 3-state window. These levels include the low signal voltage threshold of 1V and the high signal voltage threshold of 75% of the PWM signal’s amplitude. The window between 1V and 75% of PWM amplitude is the 3-state window.

Minimizing Noise on the PWM Signal

To minimize high frequency noise on the PWM signal, a small RC filter can be added that is placed close to the driver but before the optional pull-down resistor (R1). An RC filter will affect the operation of the 3-state circuit by extending the hold-off time by the RC time constant when going into the 3-state mode. It is recommended that provisions be made for this RC filter and pulldown resistor (R1)  for initial designs so that they can be added if needed.

More information regarding the 3-state input feature of the TPS28225 can be found in Section 6.3.4 3-State Input of the datasheet.