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TPS62912: TPS62912 use in sync mode with clock provided from FPGA it tries to power up

Leonid Sapozhnikov
Prodigy 50 points
Part Number: TPS62912

I am trying to use TPS62912 to power FPGA, but I want to run it in sync mode after initial phase of powering up.
What is correct sequence to start it with enable only and then add sync logic when FPGA will be functional. Is it possible since internal configuration is read at initial power up?
Basic question is it possible to go from enable to sync at any moment and still have proper functionality.
Or it will not be possible due to start up conditions which limit to only enable or sync operation. Could find clear reference in the datasheet.

Thank you.

  • 0
    TI__Genius 9480 points

    Hi 

    Yes, you can use S-CONG pin and EN/SYNC pin to meet your requirement.

    For clear reference, pls check the chapter 7.3.1-7.3.3.

    Let me know if still any concern. 

  • 0 in reply to Young Zhao
    Prodigy 50 points

    I expect that my task could be possible, but in sections you are referring  there is no any indication that board can  start with enable and then switch to synchronous operation without powering it down
    I can see that configuration changes "if EN is pulled below 200 mV or if VIN falls below UVLO". But I will start with enable is on.
    And selection of R= 27.4 kΩ. Since no synchronization. is it going to work at this setup with internal oscillation.
    This power will start FPGA which will change enable to desirable synchronization frequency.
    And when this change will happen will external oscillation will substitute internal one.
    I see reference to another condition when it describe transition from clock to enable. "When the clock signal changes from a clock to a static high, then the device switches from external clock to internal clock" it confirm that this transition is working, but in my case enable  is the first and then sync applied.
    So, does it work? It is not clear.
    Once again I am trying to use enable to power up FPGA and then with FPGA logic to apply synchronization signal of DC-DC synchronous operation for low noise system Please clarify my concerns. Thank you, Leonid