For detect time delay (td-sense), for example, when CCTS_EXT: 1μF is used, there is a slight difference between the value on page 5 of the data sheet and the calculation formula on page 14.
・Page 5: 619ms
・Page 14: 655ms
Am I correct in assuming that the calculated value is a more accurate delay time?
Would you please let me know the reason why the difference is occurring?
Best regards,
Satoshi
Hi Satoshi-san,
Thanks for your question. For clarification, Typical values comes from generally what we measured on the bench, and the difference come from the equations cover for more cases. They should be still very similar as in this case.
I got some test bench results to explain your question. Please find them in below. Even if CTR = 0.1 uF for the both cases, I got different reset delays.
When Vdd = 3V, measured tctr = 61.78 ms
When Vdd= 5V measured tctr = 64.18 ms
The sense or reset delay varies according to the external capacitor (CCT_EXT), CTS and CTR pin internal resistance (RCT) provided in the Electrical Characteristics table, and a constant. And the test conditions such as input slew rate and/or VDD level may also affect role on delay as in seen above.
I would recommend using equation 1 (in 6.3 User-Programmable Sense and Reset Time Delay section) to calculate the typical time delay. And you can also use equation 6 and equation 7 for the min and max reset and sense delay you can get. This way you can have a better understanding on what to expect for the delay.
I hope this helps!
Best Regards,
Sila
Hi Satoshi-san,
If you look at the datasheet, VTH_CTS and VTH_CTR is defined as 0.73*Vdd.
By using RC equations, we get -ln(0.27).
0.73 * Vdd = Vdd (1 - exp(-t/RC) ) -> t = - ln( 1 - 0.73 ) * 500k * CCT_EXT = - ln( 0.27 ) * 500k * CCT_EXT
They can use this equation to calculate their cap value, and then they can use that cap value in equation 6 and 7 to get min and max delay.
Can you please provide what is their delay requirement so I can assist more?
Best Regards,
Sila Atalar
Hi Sila
Thank you for advice,
Would you let me confirm about VDD condition?
I learned that the delay time varies depending on VDD, but the test condition in the data sheet was 0.85V ≤ VDD ≤ 6V.
So I couldn't determine the specific conditions.
I would like to know the pinpoint VDD test conditions.
Delay requirement is, CCT: 150pF and tpd: 639μs (507μs_min ~ 827μs_max), VDD is 3.3V.
Best regards,
Satoshi
Hi Satoshi-san,
Thanks for sharing the delay requirements. I checked with my team and I learned that the typical value is the average value from all the VDD voltage range on the datasheet. So there is not just one test condition that I can share.
And I also want to clarify why VDD is slightly affecting the reset and sense delay. If you look at the functional block diagram CTR and CTS pins are internally pulled up to VDD. That is why there is a sight chance when VDD change.
I hope this helps! Let me know if you have any questions.
Best Regards,
Sila Atalar
Hi Sila san
Thank you for kind support,
I looking forward to your update.
Sorry, I found mistaken information below;
"Delay requirement is, CCT: 150pF and tpd: 639μs (507μs_min ~ 827μs_max), VDD is 3.3V."
⇒ CCT:150pF is not need, requirement is only tpd: 639μs (507μs_min ~ 827μs_max) and VDD is 3.3V.
By the way, equation (6) and (7) are described about td_sense, Is it correct that this Min~Max ( - ln( 0.29 ) to - ln( 0.25 )) value can also be applied to td?
Best regards,
Satoshi
Hi Satoshi-san,
No worries! Thanks for the clarification.
To be clear for your delay requirement, td: 639μs requirement, you should be using 900 pF. ( by using equation 1 in section 7.3.2)
I don't have that exact cap value, that's why I used 820 pF instead to assist you with delay calculations and measurements.
When CCT_EXT = 820 pF => - ln( 0.27 ) * 500k * CCT_EXT + 50 us => the calculated delay is 587 us.
Please find my measured delay in below.
td = 583us
tsense = 593us
(Vdd =3.3V, CTS =820 pF, CTR =820pF)
I hope this gives you clarification. Your delay requirement pretty wide (507μs_min ~ 827μs_max) , so please feel free to use a cap value between 800pF - 1.1nF. The delay should be in that range.
Best Regards,
Sila Atalar
