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TPS717: Simulating Noise in TPS71750 LDO

Johnathan Williams
Prodigy 10 points
Part Number: TPS717

Hello I am using the TPS71750DSER LDO regulator in a PCB design. I am trying to simulate the noise at the output in LTSPICE simulations.

Does the model file for the part, "TPS71750_TRANS.lib" properly incorporate the noise into the part during LTSPICE simulations?

I am running both .NOISE and .TRAN simulations and I wanted to make sure that the actual noise in the real life part is being properly simulated in the overall circuit or if I will have to instead introduce a second noise source or custom noise source and add that to the circuit?

Thank you,

Johnathan Williams

  • 0
    TI__Mastermind 36555 points

    Hi Johnathan,

    The models by themselves do not simulate noise.  You can likely add components around the LDO to build a noise model, however due to LTSpice legal license agreement I'm unable to offer assistance with this simulator.  You can also simulate the LDO using a free copy of PSpice for TI available from TI.com.

    Thanks,

    Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 10 points

    Does the PSPICE model for this part also incorporate noise into the simulations?

    Also from the data sheet for this part is there a way I can extract or extrapolate the values for white voltage noise, voltage flicker noise, white current noise, and flicker current noise? 

  • 0 in reply to Johnathan Williams
    TI__Mastermind 36555 points

    Hi Johnathan,

    The PSpice model is the model you are pulling from TI.com, and I assume this is the model you used to import into LTSpice.  It is this model that TI provides which does not incorporate noise into the simulation.  The noise measurement on the datasheet is the summation of all noise artifacts (all that you listed) and we do not have a method to splitting out the specific impact of each noise type to this noise measurement.

    Thanks,

    Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 10 points

    Understood. So as mentioned I'm using the TPS71750DSER version of the product. So basically I have a 5.7V input with an output voltage of 5V. Our noise reduction capacitor is 10nF and there is a 1uF capacitor at both the input and output of the part. Roughly the total amount of current I'm drawing from that LDO is 35mA. Also our expected signal Bandwidth is from 15kHz to 300kHz instead of the listed of 100Hz-100kHz. On the data sheet I see that the total noise (summing all individual noise sources from white noise, flicker noise etc.) from 100Hz to 100kHz is 30uVrms. Would this value still apply for the LDO implementation we're doing with 5V output and 35mA current draw or should I use a different noise Vrms value? 

  • 0 in reply to Johnathan Williams
    TI__Mastermind 36555 points

    Hi Johnathan,

    Keep in mind that the dominant noise source in an LDO is the voltage reference itself which is gained up by the error amplifier in accordance with your output voltage settings.  So you will want to use this EC table snippet to help calculate the noise in the industry standard frequency range (either 10 Hz - 100kHz or 100Hz - 100kHz):

    We don't have this device characterized above 100 kHz.  Do you have a target noise spec you need to meet? We might be able to suggest a newer device with measurements above 100kHz.  If you need to use this LDO, it will be easier if we take a measurement for you.  What is your expected output capacitance?

    Thanks,

    Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 10 points

    The capacitor connected to the output pin of the LDO is 1uF.

  • 0 in reply to Johnathan Williams
    TI__Mastermind 36555 points

    Thanks, I saw you mentioned that in your previous response and I missed it. 

    Do you have a noise target you are trying to meet across this frequency range?

    Are you using the adjustable version or the fixed version of the LDO?

    Thanks,

    Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 10 points

    I am using the fixed version. The TPS71750DSER with a 5.7V input and 5V fixed output. I have a cascade RC filter or 2 stage RC filter with -40db/dec attenuation (2 poles basically). I want our filter to at absolute minimum provide at least -79dB of attenuation at 300kHz. The additional noise from the LDO should be no greater than 1nV/sqrtHz across 15kHz to 300kHz.

  • 0 in reply to Johnathan Williams
    TI__Mastermind 36555 points

    Okay thanks, we'll take a look to see if the LDO can meet this target noise across this frequency spectrum.  We'll likely test with the adjustable version as well because we can add a Cff (feedforward capacitor) across the top setpoint resistor which has the net effect of lowering the noise across frequency.  We have the EVM's in our local lab, but please allow 3-5 business days for a measurement and response.

    Thanks,

    Stephen