Dear Team,
can you please review following schematics ( which one would you recommend)
Best Regards,
d.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Dear Team,
can you please review following schematics ( which one would you recommend)
Best Regards,
d.
Hello d_zero,
I would recommend the second schematic at the bottom.
The bigger input capacitance is providing more headroom for the DC bias effect of ceramic capacitors. The effective capacitance is lower than the nominal value when a voltage is applied. Please check the manufacturer's DC bias curves for the effective capacitance vs DC voltage applied.
Same is valid for the output capacitance.
You could also consider a lower resistance in the FB voltage divider, but 100kOhm are also OK. Lower values of FB resistors achieve better noise immunity, and lower light load efficiency, as explained in the Design Considerations for a Resistive Feedback Divider in a DC/DC Converter analog design journal.
Please also check chapter 9.3.1 Voltage Tracking in the datasheet for the signal requirements at the SS/TR pin.
Best regards,
Andreas.
Hi Andreas,
what do you mean by:
" Please also check chapter 9.3.1 Voltage Tracking in the datasheet for the signal requirements at the SS/TR pin." ?
i checked and the SS can be floating then:
Leaving the SS/TR pin not connected provides the fastest start-up ramp with 160 µs typically
Best Regards,
d.
Hello d_zero,
If this is the intended behavior, then you are right and it is OK to leave SS/TR pin not connected.
I somehow thought it will be connected to an external signal for tracking.
Best regards,
Andreas.