Other Parts Discussed in Thread: TPS7H4001QEVM-CVAL
Hello TI E2E,
We’re using 4xTPS7H4001-SP (Flight No. 5962R1820501VXC) in a 1xMaster + 3xSlave configuration to realize a 4 channel 72Amp design.
The PCB is extremely space constrained, and the device being supplied has a 400micro-ohm impedance target.
To satisfy the various constraints we currently have the master and 3xSlaves placed in a “Horse-Shoe” arrangement as shown in the screen shot below.
Because this is a deviation from the traditional “in-line” placement of the master and 3xSlaves, e.g. the placement on the TPS7H4001QEVM-CVAL Evaluation Module, can you please advise if the “Horse-Shoe” placement shown below is viable or if it has any inherent problems we should be aware of and need to mitigate?
Thank you,
-John
