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LM5069: Fault Timer

Part Number: LM5069

Hi,

We're using the LM5069-2 and planning to use similar design to limit/control the amount of inrush current. We're using the dv/dt controlled startup.Upon revival of the design, I've noticed a possible error about the Fault timer.

Q1: In the video https://www.ti.com/video/4609077122001 correct behavior is described in the early part of the video where it is highlighted to use a fault timer time which is always larger than the expected time to charge the expected capcitance at maximum input voltage. At around 4:00 it is suggested by the quickstart excelsheet to use Ctimer = 180nF which would give an expected fault timer at about 3.4ms. At 9:20 however it is suggested to use a fault timer of about 1ms which seems very odd as this is shorter than the typical expected start time of 1.65ms.

Any comments on this? (Perhaps not all relevant here but the EVAL kit also uses a much larger capacitor (560nF).

I had to look this up in our existing design where physical measurements of our board seem to indicate a charge time of about 40ms, but (incorrectly?) the excel sheet Ctimer = 47nF which gives an actual fault time of about 2.2ms. I was then curious to how our earlier design even was allowed to charge up at all. Providing scope-plot with following curves:

  • C1 Yellow: Vout (5V/div)
  • C2 Green: Series current clamp to the DUT (200mA/div)
  • C3 Orange: Input voltage 0-31V step (5V/div)
  • C4 Blue: Voltage of Ctimer (0.5V/div)

From the graph we can clearly see during 40ms the first insertion time delay. 

After about 40ms, the dv/dt is controlled which results in an controlled inrush current of about 500-700mA. After an additional 40ms, Vout equals Vin and remaining stuff downwards is tuning on etc. It is working as suggested, but could perhaps be improved by addition of a capacitor on the power good pin to delay further downstream consumers a little bit.

The voltage of the Ctimer (blue) correctly operates as expected during the insertion time delay, but does not get charged during the (current limiting/power limiting) region t2.

Any comments on this? 

Including excel sheet and oscilloscope plot. Appreciate all input to increase my understanding of the circuit.

Best regards //O

LM5069_Design_20240319.xlsx

  • We will get back to you tomorrow.

  • Hello Avishek. Any update available?

    Have a nice week //Oscar

  • Hi Oscar,

    Sorry for the delay,

    Please refer to this below app note. 

    Robust Hot Swap Design (Rev. A) (ti.com)

    When the external soft start capacitor is used, the device does not enter into current limit or power limit during startup as the inrush current flowing through the MOSFET is much less than current limit or power limit. Hence, timer won't run during startup. 

  • Hi Avishek and thanks for reply.

    Oh okay that makes sense I guess. The dv/dt controlling circuitry is limiting the inrush current to a value which is less than the current limit or power limit so that the timer never starts then. Hmm I need to evaluate if this can cause any concerns if the FET is stays in this region for a long time since the protection mechanisms are somewhat 'blinded' then. First guess is that I do believe it should be okay however. 

    Did you have any input to my first question that the information given in the video seems incorrect at 9:20(?) or have I misinterpreted? Otherwise the video is good and explinatory.

    The links provided earlier points towards the quickstart calculator and not the app note ( https://www.ti.com/lit/an/slva673a/slva673a.pdf )

    I'll set the issue as resolved after your reply.

    Best regards

    //Oscar 

  • Hi Oscar,

    Sorry for my mistake. Please see the below app note link.

    Robust Hot Swap Design (Rev. A) (ti.com)

    When you are not using the external soft start capacitor, the fault timer duration must be greater than the start-up time to have successful powerup. But, when the external soft start capacitor is used, the fault timer duration can be less than the startup time as the fault timer does not run during startup with an external soft start capacitor. 1.65ms is the startup time with power limit. Hence, 180nF is selected as a fault timer capacitor to have the successful startup with some tolerance. While using the external soft start capacitor, the fault timer duration can be selected independently.