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LM74502-Q1: schematic review

Part Number: LM74502-Q1

Hi team,

My customer is evaluating LM74502-Q1 in their project, could you please help review and give some comments? Thanks.

When using the LM74502-Q1 as a reverse connection protection solution, customer find that it has not been able to achieve the reverse connection protection effect.

Experimental conditions: Power supply: 13V, 20A current limit.
The max DS voltage of both MOS is 40V, and the regulator diode is regulated at 15V.

Regards,

Ivy

  • Hi Ivy,

    The schematic looks fine. Although, you can remove resistor and diode from gate to source as the FET is rated for 20V and controller can drive till VGS ~13V only.

    "customer find that it has not been able to achieve the reverse connection protection effect."

    Can you share waveforms of the test case.

    Plot VS, VOUT, VCAP, GATE

    Regards,

    Shiven Dhir

  • Hi Shiven,

    Please see the test waveforms.

    The anti-reverse MOS started to break down around 3s after turning on the reverse 

    Regards,

    Ivy

  • Hi Ivy,

    Thanks for the waveforms.

    The anti-reverse MOS started to break down around 3s after turning on the reverse.

    In the waveform I can see, as soon as negative voltage is applied, VOUT is also pulled low which is not expected. Where did the 3s figure come from?

    Also, can you load VOUT? say 100ohms. 

    Regards,

    Shiven Dhir