LMR36015: Two Buck sections with a floating GND

Hi Kaushalya,

Thank you for reaching out.  I am afraid it would not work, because current always flow in a closed loop, but I don't see a path for the current coming in to the GND to flow out of it.   Or your schematic is not complete?  

Thanks,

Youhao

Hi Youhao,

Thanks. What you mean is current from the bridge output to GND? The current path is via the output, Vout2. If I simplify the input bridge to a single diode, this is evident.

Since AC_A net is connected to Vout2, the negative terminal of C_BULK is at Vout2, with respect to 0V. Then Vin to first regulator is V_BULK + Vout2. I have tried this with a single regulator section and it seems to work. What I am not sure is this dual regulator design will work or not. 

Cheers,

Kaushalya

Hi Kaushalya,

Sorry I may have missed something.  See your circuit node 0V.  All circuit branches have current flowing into the 0V node, but where is the path for the currents to flow out of the 0V node?  

Thanks,

Youhao

Hi Youhao,

Thanks again. My understanding is that switching currents and the load currents will flow into the AGND/PGND pins of the regulators as follows. Is my understanding not correct?

Cheers,

Kaushalya

Hi Kaushalya,

Could you show me how to get Cin charged up?  It must be charged up first before the circuit can start switching.

Thanks,

Youhao

Hi Youhao,

If you rearrange Cout2 (output cap of second regulator) as above, Then you can see the current going through Cin1, Cout2 and returning to AC_A, in one half cycle.  Also there is the Rload at output of regulator 2. 0V is actually Vout2 below RC_A voltage. 

Cheers,

Kaushalya

Hi Kaushalya,

Very sorry for being slow in understanding such an approach. Please allow me to explain my concerns.  What ever you do, the IC must meet the proper voltage settings wrt its GND pin. 

1. Cin1 and Cout2 are in series during initial charging, their values would determine their share of the total voltage. Note the capacitor tolerances.  This does not guarantee EN to be greater than the threshold, thus not guarantee the start of switching.

2. Vout2 would be initially negative wrt to the IC GND pins, because Cout2 is reversely charged. This may violate our datasheet's abs max rating.  

Hope this clarifies.  Or I mistook something in my understanding?

Best Regards,

Youhao

Thanks again Youhao. Yes this is an unusual arrangement. I want this because I am using this power supply to trigger a triac gate. I am trying to keep negative gate current to use quadrants ii/iii of the triac.

1. Vin is V_BULK - Vout2, isnt it? Vout 2 in my case is 3V3 and V_BULK is like 32V. So my understanding is EN should be enable the switcher. 

2. This can be an issue. When I further check, for less than 10ns, VSW can be subjected to -3.5V. I tried simulating this circuit and I can see the negative voltage is within 10nS. However, have to do actual bench test to substantiate this. The simulations take ages to run so no easy.

Please have a look at https://www.tij.co.jp/jp/lit/an/slva910/slva910.pdf This is also similar to what I am trying to do I guess. 

Cheers,

Kaushalya

Hi Kaushalya,

I think part of the confusions that I had started with your first couple of schematics, in which the return goes to the front of the rectifier bridge. 

After drawing out the hidden MOSFETs, I can see the charging path to Cin at the beginning: The current will flow from AC_A down Cin to your "0V" node, the takes the body diode of the internal low side FET of the 2nd IC, then flow out of its SW, then through the 2nd inductor to the Vout2 , then come back to AC_B. Once Cin is charged up, it will start the first IC, and establishes Vout1, which enables the 2nd IC to establish 3.3V.  So, should VOU2 returns to the negative terminal of +C_bulk?   If you tied to the front of the bridge, your bridge would effectively to operate in half wave, do you agree? 

Beside, I don't know your system grounding.  When you use floating, such a configuration does not have a floating ground. The ground that you referred to basically 3.3V plus a diode drop below the system ground of the AC system.

Note that you may consider to add a Schottky diode clamp across VOUT2 output as shown in the App notes that you referred to, to prevent SW from exceeding the negative voltage rating. 

Thanks,

Youhao

Hi Youhao,

Good point about the body diode of regulator 2 low side switch. I guess I can do as you propose as well. Also I think we cant use a full bridge as you mention. So I will have a half wave rectified Vin as shown in later schematics.

The only requirement was to keep the 0V below AC_A by Vout2 (0V = AC_A - Vout2). The AC_A is connected to a Triac MT1 and gate is driven by a GPIO output of a MCU, which is powered from Vout2. The 0V is the system GND. By having 0V below AC_A by Vout2, I can keep the Triac operate in Q2/Q3 (Gate current negative). 

Otherwise if I configure the power supply in traditional manner, then the Triac will function in Q1/Q4 or positive gate current. I cant use any Triac drivers due to the BoM cost restrictions.

My MCU can source max 8mA, whish is enough to operate the Triac in Q4. As long as I use traditional Triacs, this is not an issue. So wiring the two power supplies without connecting the AC_A to Vout2 is also an option. 

What would you suggest? 

1. Connect AC_A to Vout2 and operate Triac in Q2/Q3

2. Don't connect AC_A to Vout2 and operate Triac in Q1/Q4

Cheers,

Kaushalya

Hi Kaushalya,

It's you decision but I would suggest  your option 1 to meet you requirement if Q2/Q3 is what you want to operate in.  However, I think you can still use a full bridge but you need to connect VOUT node to Cbulk's (-) terminal after the bridge, as I drew in my May 28th reply.

Can this be a quick test if you already have each stage built?  Experiment has the final say :-)

Best Regards,

Youhao

Hi Youhao

I am in favor of Option 1 as well. What I am not certain is about stability of the buck in line transitions like. Simulations takes ages. Regarding the full wave rectification with bridge, the AC_A will be disconnected from Vout2 in one half cycle isn't it? This is when AC_A < AC_B. So within this half cycle, my requirement of 0V = AC_A - Vout2 is not met. So have to use half wave rectification with a single diode. What do you think?

I have ordered two dev boards to try this out as you say - experiment has the final say :D I will update what I find here.

Cheers,

Kaushalya

Hi Kaushalya,

I might have misunderstood your purpose. Now I suddenly realized that you would like to float the output on top of AC_A in front of the bridge rectifier.  Then you do not need a bridge there, for one leg is virtually wasted. Single diode from AC_B to C_bulk should be the way to go.  Honestly  I never did something like such configuration, but I think your concept should work. 

Looking forward to your updates. 

Best Regards,

Youhao

Much appreciate all your thoughts Youhao. Sorry for not being clear enough about the requirements. I tried the two series buck modules using two MICROE BUCK 11 modules. I changed one for 12V and the other is at 3V3. Used one diode for rectification with 100u bulk cap. Set the step load for 700mA and 3V3 regulator output was stable. It is not as easy for me to simulate a line transient, but will try that as well. 

Vout2 pk-pk ripple is about 40mV @ 700mA load. 

Cheers,

Kaushalya

Hi Kaushalya,

Thank you for the info.  I agree with you on the sim time, and I would run a line transient test for more convincing evidence of performance.  By the way, 40mV ripple is not bad for a 3.3V output, and hope this meet your spec.

Thanks,

Youhao