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LMG1210EVM-012: LMG1210EVM-012

Harsh Rana
Prodigy 80 points
Part Number: LMG1210EVM-012
Other Parts Discussed in Thread: LMG1210,

Hi,

I'm a little bit confused while analyzing designs from TI.

I was facing an issue of huge power supply ripples while driving half bridge circuit using LMG1210 (Even with a 7.4V lipo battery as input). Then I come to know the solution as using ceramic decoupling. capacitors.

Reference: https://www.ti.com/lit/an/slta055/slta055.pdf?ts=1711689333008

For my application, I required Vin(max) 100V, Iout(max) 5A, Duty Cycle 2% to 98% (assuming 50%), fsw 1MHz, Vp(max) 100mV. The value of ceramic capacitance comes out to be 12.5uF as per the equation (1) of the reference given above.

Now the controversy starts with the development board of the same IC : LMG1210EVM-012 (https://www.ti.com/lit/ug/snvu572/snvu572.pdf?ts=1711691344661&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FLMG1210EVM-012%253FkeyMatch%253DLMG1210)

The development board is claiming upto 10A current, fsw 1MHz (Typical - Same as I'm using). But the development board is using (C3 -1uF*1  ||  C7,C10 - 0.22uF*2  ||   C4,C5,C12 - 0.022uF*3). That combined capacitors is valued 1.1144uF. That's not even close to 12.5uF as per the calculation of the given reference. Can anyone suggest me what valued ceramic capacitors should I use?

  • 0
    TI__Genius 13690 points

    Hi Harsh,

    Thank you for posting to E2E. One of our experts will get back to you shortly.

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    TI__Genius 12275 points

    Hey Harsh,

    Thank you for your patience as our team was out of the office this past Friday on holiday.

    Looking at Equation 1 from the Input and Output Capacitor Selection application report, these are related to load capacitors where Iout is the steady state output load current. This is very dependent on the switching frequency, duty cycle, and Vp(max). What is preplaced on the EVM needs to be suitable for a wide range of operating conditions and that is why C6 was left unplaced (as well as C17 and C20). With the EVM you could add the needed capacitance based on the needs of your system to satisfy Equation 1. The equivalent capacitance for the EVM on Vbus is 1.506uF as these are all in parallel.

    For your application, the 12.5uF capacitance is accurate due to the 100mV Vp(max) requirement and the 1Mhz operating frequency at 50% duty cycle.

    Let me know if there are any questions.

    Thank you,

    William Moore

  • 0 in reply to William Moore
    Prodigy 80 points

    C6 is the input Electrolytic capacitor, C17 is output electrolytic and C20 is output ceramic capacitor in LMG1210EVM-012.

    I'm concerned over input ceramic capacitor selection which are (C3+C7+C10+C12+C4+C5). For my application, my output section is ok, the input section have bulk electrolytic capacitor, just having confusion on selection of minimum input ceramic capacitors, as the input is having crazy ripples on driving the circuit with 1MHz operating frequency and very sharp rising and falling time. I'm currently using lab bench power supply as input. So is 12.5uF is minimum required input capacitor or 1.1144uF is enough?

  • 0 in reply to Harsh Rana
    TI__Genius 12275 points

    Hey Harsh,

    For your operating conditions, you will need to add capacitance to achieve the 12.5uF minimum capacitance. This should help with the ringing that you are seeing on the input. With the sharp rising and falling edges, you are likely to see overshoot/undershoot as well.

    You are welcome to share waveforms here of the ripples you are seeing as well.

    Let me know if there are any further questions.

    Thank you,

    William Moore

  • 0 in reply to William Moore
    Prodigy 80 points

    I've blown up few LMG1210 ICs due to human error. I'm waiting for new stock to arrive. That's why I cannot show you the actual ripples that are occurring on input voltage. I've done the Spice simulations for the schematic in third party software and the results are perfect. You can go through the schematic that I'm working on and the references for the same. Decoupling capacitors are missing in the schematic.

    I'm also attaching a recorded video of the output waveform of the system. At higher voltage (>20V), you can notice that the output waveform distortion starts happening. That's because of the input supply is getting too much noisy.

    Schematic: https://drive.google.com/file/d/14AVw8GwC_Nxe3WnMu-t2NF9v9Fl2N4zz/view?usp=sharing

    Reference: https://www.ti.com/lit/ug/slau508/slau508.pdf?ts=1712121580363&ref_url=https%253A%252F%252Fwww.google.com%252F

    Recording: https://drive.google.com/file/d/15sLuPdKBXymEVfCLBwZOdr9OOJ-tcZA0/view?usp=sharing

  • 0 in reply to Harsh Rana
    TI__Mastermind 22275 points

    Hello Harsh,

    William is out of the office for the remainder of the week. I did try to view the recording, which I assume has the waveforms you are referencing. For some reason I did not see your file on Google drive although I did get access.

    If there is excessive ripple and noise on the power train HV input that could certainly impact the output ripple. If you have a picture or pdf of the waveforms that you can attach I could review, while William is out.

    Regards,

  • 0 in reply to Richard Herring
    Prodigy 80 points

    My next version of PCBs and BOM are on the way and may take 15-20 days. If the issue still remains with the correct decoupling ceramic capacitors also on that board, I'll come back with pictures.

  • 0 in reply to Harsh Rana
    TI__Mastermind 22275 points

    Hello Harsh,

    Thank you for the update. As I mentioned previously, William will be back in office after the weekend, and we can address any questions when you verify the new board layout and waveforms.

    Regards,