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CSD17577Q5A: Normal Thermal Performance

Part Number: CSD17577Q5A
Other Parts Discussed in Thread: CSD17579Q5A


I am currently using the CSD17577Q5A in a synchronous buck battery charger
Specifications are below:
Vin = 19.7V

Vout = 13.8V

Iout = 10A

Fsw = 350kHz

PCB Stackup:
6 layers, Surface finish HASL-Lead Free
L1 2oz = SIG/PWR/GND

L2 1oz = GND

L3 1 oz = SIG/PWR/GND

L4 1oz = PWR

L5 1oz = GND

L6 2oz = SIG/PWR/GND

Currently with our first prototype everything works fine, other than the concern I have for the temperature rise of the HS mosfet in room temperature
At full load of 10A and 13.11V output the HS mosfet gets up to 72.3C (temperature measurement was made on a thermal imager on the top side of the mosfet case) . Based on the SYNC mosfet calculator sheet you have the estimated total power loss of the mosfet is about 1.3W

Currently there is copper on all layers(except solid GND layers underneath this mosfet with thermal vias

Based on this information the estimated Junction thermal ambient resistance is about 40.4 C/W (assuming 2.8 C/W junction to case temperature)

Couple of questions I had regarding this was

1) for this mosfet have you been able to reduce the Junction to ambient thermal resistance by much more than this in a practical application(assuming my estimated calculation is correct)?

2) Do you see this as a concern that the mosfet is getting this hot during these conditions? Our product will be in an enclosure so the air within the enclosure will rise to about 45C

Any suggestion/concerns that you may have will be greatly appreciated  

  • Hello Visaacan,

    Thanks for your interest in TI FETs. Please see the technical article at the link below for more information on how TI tests and specs thermal resistance in the FET datasheet. RθJA and RθJC are measured on a standardized PCB on 1in² Cu and on a minimum pad size as shown in the datasheet. TI only guarantees RθJC (measured to the drain pad) since RθJA is highly dependent on PCB layout and stackup. How did you determine RθJA to be 40.4°C/W in your application? The primary path to remove heat from the package is thru the thermal (drain) pad and into the PCB. The estimated RθJC to the top of the package is 45°C/W (from earlier simulations) compared to 2.8°C/W for RθJC (bottom). Assuming ~90% of the heat is removed thru the thermal pad, then about 10% is dissipated thru the top of the package. The estimated junction temperature rise from the top of the package: ΔTJ = 0.1 x 1.3W x 45°C/W ≈ 6°C. Using these assumptions, the case temperature should be within about 10°C of the junction temperature. For your application, at 45°C ambient, the estimated top case temperature = 72.3°C + 20°C (assuming room temperature = 25°C) = 92.3°C and estimated TJ = 92.3°C + 10°C = 102.3°C < TJmax = 150°C with margin. In general, the max power dissipation for the 5x6mm SON package is about 3W depending on board stackup and layout. The dissipation in your application is only about 1.3W which is within the package capabilities. These are only estimates but based your top case temperature, it should be OK in your system with some margin to spare.

    Best Regards,

    John Wallace

    TI FET Applications

  • Hi John,

    Thank you for the detailed response the estimate of 40.4 C/W was based on solving for RθJA while using RθJC (bottom) (did not realize this for bottom of the package thanks for the clarification)

    With this FET and the 1.3W power loss do you think I could decrease the case temperature further? Or is this typically the type of performance you have seen for this package?

    Side question with this mosfet currently during switching of the buck converter the VDS voltage experiences a undershoot of about  -4.6V when switching off for about 10ns would this be a concern as its falling below well body diode voltage? 

    Thanks again for your help,

  • Hi Visaacan,

    To reduce the case temperature, you should be using thermal vias in the drain pad on the PCB that go to internal/back side copper shapes connected to the input voltage to the buck converter. You might also consider using a different low side FET such as the CSD17579Q5A. This increases the loss in the sync FET but reduces the loss in the control FET. For a high duty cycle such as this, the low side FET can be a higher on resistance/lower gate charge device which helps to reduce some of the losses in the high side FET. If you would like to share your PCB layout, I would be happy to review it.



  • Hi John,

    Is it possible I could sent the layout via email or direct message?
    And if so what format would be best gerbers?

  • Hi Visaacan,

    You can email me directly: What PCB layout tool do you use? I have Allegro and Altium readily available along with other viewers. I'm not as good with gerber files but I can work with them.