TLV1117LV: TLV1117LV LDO Layout Review/Comments

Schematic for reference:

Looking forward for your guidance.

Hello,

Thank you for your schematic and layout review request. 

Please allow me 2-3 business days to review your request.

Best Regards,

Hannah

Hello,

Overall, the schematic and layout look good according to specification.

I just have a few recommendations:

For the schematic:

Everything looks according to specification.

For the layout: 

We recommend increasing your GND plane for thermal performance.

Additionally, we recommend a strong power plane on the input.

Please let me know if you have any additional questions or concerns.

Best Regards,

Hannah

Hannah Grace said:

Additionally, we recommend a strong power plane on the input.

1. Can you elaborate more on this suggestion?

2. I would like your review on the "loop shape" formed by the VOUT plane marked as "Solid Power Loop" from the decoupling perspective.

Hannah Grace said:

1. We recommend having a thicker trace / a plane on VIN to help with LDO performance.

Okay, got it, I will increase the trace to a VIN plane

Hannah Grace said:

2. The Solid Power Loop looks good from a decoupling perspective. 

So to confirm - no issues with solid traces forming a loop from the other side of the VOUT & supplying the power to the MCU/BAW Oscillator - no loop issues here?

Hannah Grace said:

3. Is GND pin (2) tied to the GND plane? As of right now it does not seem to be tied to anything.

Yes, I will be adding 2x Vias to the bottom ground plane to the C3, thank you for pointing it out.

2. I don't see any immediate issues with the solid power loop.

Hello Hannah,

This maybe elementary - But for better performance do we need to decouple the other VOut Pin (ie Pin2) of the TLV1117LV? Can you guide on this?

Your design looks fine to me. Here is a typical layout for this part: 

In the layout, we recommend keeping the input and output capacitors as close to the part as possible, which it looks like you have done in your design. 

Hello Hannah,

Kindly guide us about the requirements for Reverse Current Protection - I mean how large the Cout has to be to implement an external Schottky Diode based Reverse Protection? Due to limited board space - we would like your valuable practical guideline on if we need to implement reverse current protection given our Cout is 10uF.

Hello,

For ease of rework, it may be valuable to use 0805 output capacitors. The 0805 cap should work fine with the external Schottky diode. 

Best Regards,

Hannah

Hello Hannah,

My question was for/above what value of output capacitor do we need to mandatorily use an external Schottky Diode?

For instance one hypothesis might be - a minimum of 1uF Output Capacitor might not require a Schottky Diode for safety from reverse current but maybe a 10uF might need one for safe operation..

Kindly share some practical insights on this aspect of TLV1117LV LDO.

Hello,

Please see LDO Basics: Preventing reverse current for additional information. I am unsure about what Schottky diode placement you are planning to use, but I believe this paper may be able to clear up some of your questions.

Best Regards,

Hannah 

Hello Hannah,

My question is very specific when using Schottky Diode in any of the two configurations - do we need it when we are using a 10uF Cout MLCC?

We do not have board space for accommodating this diode, hence our query. Kindly share specific guide or allow other E2E engineer who can help with our query given the details shared in this post.

Hello Hannah,

Thank you for the update, this is much more actionable insight for us to incorporate in our designs. I appreciate your assistance!

Absolutely. I will be closing this thread out for now. Please let me know if you have any additional questions or concerns.

Best,

Hannah