LM5146: LM5146RGYR

Hi Bob,

Apologies for the delay.

Here are some comments:

1. You may want to use different high-side and low-side FETs (depending on Vin, Vout and where optimization should occur in the Vin range). Use the quickstart calculator in tandem with the NexFET selector tool: https://www.ti.com/tool/SYNC-BUCK-FET-LOSS-CALC. No harm checking WEBENCH as well.
2. NC pins of the controller can be tied to GND (for better heat spreading).
3. C10 6.8pF should go from ILIM to PGND (not from SW as shown).
4. Check compensation values with the quickstart. Ensure that the correct derated value for ceramic Cout is entered. 5 x 22uF/25V may derate 40-60% in the 8.4V-16.8V range. Higher Vout is worst case, as it results in a lower effective Cout and thus higher crossover (for a given compensation circuit).

Regards,

Tim

PS: If Vin-max = 60V, then you can use the LM5145 75V input version.

LM5145RGYR, see https://www.ti.com/product/LM5145#order-quality 

You can use Murata's tool to check the effective capacitance of the ceramic at a given voltage: https://ds.murata.co.jp/simsurfing/mlcc.html?lcid=en-us&jis=false

Here is the plot for a 22uF/25V/1210/X7R at room temp:

Hi Bob,

The LM5145 is lower cost, hence that suggestion. They are pin-to-pin compatible, so you could change in future as well if needed.

In terms of the MOSFETs, the high-side FET has all the switching loss, so higher Rdson (lower capacitance) is possible. And the low-side FET is conduction loss dominant, especially for large step-down ratios, so it can be lower Rdson. I would stick with 5 x 6mm MOSFETs - take a look at the LM5146 EVM, which is a 12V/8A/400kHz design (close to your spec).

The LM5146 quickstart calculator will be really helpful for your design - please complete and send that for review.

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Tim

In terms of output caps, I recommend using 22uF/25V/X7R/1210. The total effective capacitance will be lowest at the highest Vout setting, so design the compensation for that and then do a quick check at the lower output voltages with those values.

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Tim

Hi Bob,

Let me check email for the layout.

Are these 3 separate designs or just one with adjutable Vout? If it's the latter, then we design the compensation with highest Vout (lowest effective Cout) and then check the lower voltages with the compensation values fixed.

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Tim

Three different output voltage but one implementation - so it has an adjustable Vout, correct? Just wondering if we need to have one compensation network for all three, or if we can optimize it for each Vout setting.

Just looking at the quickstarts, I see you are not adjusting Cout for the different output voltages. Go ahead and insert the correct "effective Cout" for each output voltage setpoint, and keep the compensation network constant based on the stability for the highest Vout.

Just looking at the quickstarts, I see you are not adjusting Cout for the different output voltages. Go ahead and insert the correct "effective Cout" for each output voltage setpoint, and keep the compensation network constant based on the stability for the highest Vout.

Also, you may use 80V FETs here for better efficiency. No need for 100V device if the layout is good and Vin-max is only 65V.

I found the layout. Here are some comments:

1. The switch for the output setting looks huge - can it be reduced? The FB trace needs to be as short as possible, as this is a high impedance node very sensitive to noise (note high feedback divider values).
2. It would be nice to have an input cap on the top side as well.
3. No need for SW vias - these just put the high dv/dt on the bottom side of the PCB (facing the EMI table). SW copper should be minimized, as it is a radiating plane. See the LM5145 EVM layout, which resembles this design. More important, the SW vias disrupt the GND plane under the power stage.
4. The shunt looks quite large, 2512. Consider using a wide aspect ratio shunt for lower parasitic inductance (see EVM).

Okay, thanks Bob.

PS: looking at the three captures from the quickstart calculator in the post above, Cout should be highest at low Vout and then progressively reduce for the higher Vout setpoints.

No, what I mean is select the capacitance, then insert the correct derated value for each output setpoint. the screenshot above has 22uF for 8.4V and 44uF for 12.5V, which has to be incorrect.

Hi Bob,

This still shows 22uF for 8.4Vout, but it should give the highest capacitance based on the derating with voltage of ceramics.

My assumption is you're selecting a set of capacitors that will work with this adjustable output design, so just enter the applicable capacitance for the three Vout levels. Actually, we usually just check min and max Vout -- design the loop for max Vout and fix the compensation values when checking the min Vout with the higher effective Cout value.

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Tim

Hi Bob,

The LM5145 / LM5146 datasheet actually has some good info on compensation for voltage-mode control. I have a couple of articles on how2power.com on current-mode control as well that are worth looking at.

I'll check my inbox now to see if I got your latest layout. The LM5145 and LM5146 EVMs are actually good templates to copy from a layout standpoint. Also, the datasheet guidelines for layout are pretty comprehensive.

Regards,

Tim

Hi Bob,

Here are some comments upon reviewing "Voltage limiter V1":

1. Being the most important caps in the design, the 4.7uF input ceramics are way too far from the FETs. Bring the FETs closer together and move the 0402s cap right by the high-side FET drain. This allows closer placement of the 1210 caps. Add more GND vias at the cap return terminals. See app note SNVA803 for power stage component placement.
2. Tie NC pins of the controller to GND (better heat spreading).
3. Minimize the area of the SW copper polygon connecting the FETs to the inductor.
4. The gate and source pads of the FETs look like they could be bigger.
5. Move the SW via near the FETs such that the HO and SW traces route close to each other, effectively as a diff pair.
6. Layer 2 should be a solid GND plane under the power stage -> move the HO trace to layer 3 and route in parallel with SW on the same layer. This takes the high dv/dt SW trace off the bottom layer as well (note: the bottom layer faces the EMI table and can easily couple noise to that GND).
7. Consider adding two more vias in the DAP for the controller.
8. Keep the VCC and BOOT caps close to the respective pins of the controller (e.g. move vias closer to the controller pins if needed).

Tim

Also, take a look at the LM5145 EVM layout for reference. The LM5145 is effectively the same controller as the LM5146, just a lower Vin-max rating.