Other Parts Discussed in Thread: UCC27714
Busy with a design with the UCC27712 high and low gate driver I stumbled on the interlock time of 100 nSec
The total pulse width is 370 nSec.
The high side pulse is nice but the low side start to work after 190 nSec which result in a narrow pulse for the LO gate
Is there a way to let this IC work on about 3 MHz with proper outputs? the delay between the LO and HO I can arrange myself
Can I order this IC without interlock ?
With regards
Ronald