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LMG3522R030-Q1: LMG3522R030-Q1 Spice model

Kobi Cohen
Prodigy 10 points
Part Number: LMG3522R030-Q1

Hi,

I have tries to import the model from the part page, and use it in LTspice (created the symbol and everything usual). 

Unfortunately - when I run it with a pulse generator in the input, I don't get any drain - source pulses. 

I'd like please to see an example (in photo or file) if possible for this model.

Thanks,

Kobi

  • 0
    TI__Expert 3415 points

    Hi Kobi, 

    Currently, our model for this device has only been designed and tested to run in PSpice. We have not tested or validated the model in LTSpice. Please use the model in PSpice if available. 

    We also have validated models available for PLECS if you have that option. 

    Best Regards,

    John

  • 0 in reply to John Gomez
    Prodigy 10 points

    Hi John,

    Got it, I will try it in PSpice. 

    Thanks,

    Kobi.

  • 0 in reply to Kobi Cohen
    Prodigy 10 points

    In regards with this issue, is this model up to date? meaning, does Coss changes with drain to source voltage or it constant? if it's constant, which value?

    In addition, does this model contain the turn on / off delays in the datasheet? td(on/off)(Id), td(on/off), slew rate vs. Rdrv, etc?

    Thanks.

  • 0 in reply to Kobi Cohen
    TI__Expert 3415 points

    Hi Kobi,

    This model was developed some time ago, please see modeling info below:

    The Pspice model provided herewith can be used to simulate behavior of TI GaN in a given electrical environment to understand its operation. This model is not intended to provide estimation of power losses in the device. The model includes integrated gate driver, certain protection features and buck-boost converter for generating +5V and Vneg voltages. Additional information about what is included in this model is provided below for the reference of the user:

    1. Rds,on: Fixed ON resistance has been used; RDS,on variation with temperature is not modeled.
    2. Coss: Fixed capacitance is used in the model. Non-linear capacitance varying as a function of voltage is not modeled.
    3. Slew rate adjustment: A fixed resistor value (10kohm to 200kohm) has to be externally added between Rdrv pin and GND pin to set the FET’s drain-to-source slew rate during turn-on. The programming of slew rate by connecting Rdrv pin directly to either GND or LDO5V is not enabled in this model and such a configuration may result in convergence errors.
    4. Fault protection: Dual Overcurrent protection and UVLO protection (for Vdd, Vneg and LDO5V pins) are integrated in the model. However, overtemperature fault is not included in the model.

    Best Regards,

    John

  • 0 in reply to John Gomez
    Prodigy 10 points

    Hi John,

    Can you please send a snapshot of the model symbol in Orcad Pspice, with the periphery components connected?

    Thanks,

    Kobi

  • 0 in reply to Kobi Cohen
    TI__Expert 3415 points

    Hi Kobi, 

    See the screenshot below of the schematic in PSpice: