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BQ25504: Power management - INTERNAL forum

Part Number: BQ25504
Other Parts Discussed in Thread: BQ25570, BQ25505

Hi Team,

We are having trouble with the BQ25504RGTR PMIC module on the board. The design was originally implemented by a contractor who we no longer have onboard, and we don't know much about PMICs. Are you or someone on your team able to support? Details are below and design screenshots are attached. Thank you!

assembly_drawing.PDF

We are expecting VBAT_OK, pin 11, to be HIGH, but it is LOW, and we do not know why. We are measuring ~0 V at pins 1-13, 4.00 V at pin 14. Pins 15 and 16 seem to float between 0 and 0.4 V. What next steps should we take?

Thank you in advance!

  • Hi,

    Can you please share the schematics, the PDF that was sent doesn't seem to have loaded very well and I can't really distinguish what the schematic is meant to look like.

    Best Regards.

  • Hi Juan,

    Please see attached.

    PMIC_screenshots.zip

  • Hi Alex,

    From reviewing your schematic, there is a couple notes:

    - VBAT_UV = 2.87V

    - VBAT_OV = 3.93V

    - VBAT_OK = 2.84V

    - VBAT_OK_HYS = 3.01V

    - It is recommended that VBAT_OK > VBAT_UV so I would consider adjusting one of the two values

    It is unexpected that, if are 4 volts present on pin 14 (VBAT) that pin 15 (VSTOR) should be less significantly lower than 4V. Can you provide waveforms for your VSTOR and VBAT? Additionally, is your VSTOR pin connected to a large load, the schematic doesn't seem to indicate that there is any load connected to VSTOR which is where it is typically expected for this device. Lastly, has this been seen on more than one IC, and if so, does replacing the IC improve the issue?

    Best Regards,

    Juan Ospina

  • Hi Juan,

    Thanks for your response

    We found that our manufacturer populated R_uv1 with an incorrect resistor value. 806k instead of 698k. I don't think this would have caused the problem, but maybe I am wrong. Regardless, we want to revise the design to simplify it and continue testing with the next revision.

    We had some logic circuitry to the right of the PMIC helping to determine if our LDO should be enabled or not. It was complicating things for us, so we are removing that and have a new plan: Have the LDO always enabled as long as the battery will output power and have our MCU measure the battery (via an opamp) and determine if the system should be kept in an ultra-low power mode (we think just a few uA at most)- when the battery is below 3 V. The battery will always be a 3.7 V (2.7-4.2 V) lithium-ion/polymer battery. For this particular device, we intend to use a 400 mA battery. The load, which draws up to 130 mA, is on VDD in the schematic below.

    Because the simplified design doesn't need the VBAT_OK signal to enable the LDO, I've left it floating. And I have also removed the resistors for OK_PROG and OK_HYST.

    Because we are not using VBAT_OK, and the load (via the LDO) is connected directly to the battery rather than VSTOR, should we remove the resistor dividers at VBAT_OV, VRDIV, and VBAT_UV as well?

    Could you please review this revised schematic, for both the PMIC and LDO?

  • Hi Alex,

    I don't think this would have caused the problem, but maybe I am wrong.

    I'd agree, this shouldn't be a causing this issue if battery is at 4V. I would still recommend double checking soldering or replacing the IC as a 4V BAT should result in a 4V VSTOR.

    Have the LDO always enabled as long as the battery will output power and have our MCU measure the battery (via an opamp) and determine if the system should be kept in an ultra-low power mode (we think just a few uA at most)- when the battery is below 3 V. The battery will always be a 3.7 V (2.7-4.2 V) lithium-ion/polymer battery. For this particular device, we intend to use a 400 mA battery. The load, which draws up to 130 mA, is on VDD in the schematic below.

    This is a possible solution, though you will be losing out on BAT_UV protection since there won't be a way for the device to disconnect the battery from the load. 

    Because we are not using VBAT_OK, and the load (via the LDO) is connected directly to the battery rather than VSTOR, should we remove the resistor dividers at VBAT_OV, VRDIV, and VBAT_UV as well?

    The VBAT_OV would still be required since this controls the battery charge voltage and prevents overcharging the battery. I would recommend keeping VBAT_UV resistors as well for more deterministic device behavior. If you want to minimize current draw you can increase the values of those resistors so long as the sum of the resistances for BAT_UV are less than 10MOhms and the sum of resistances for VBAT_OV are also less than 10MOhms.

    MCU measure the battery (via an opamp) and determine if the system should be kept in an ultra-low power mode (we think just a few uA at most)

    The VBAT_OK signal could be used for this purpose, unless this external opamp method is preferred.

    Could you please review this revised schematic, for both the PMIC and LDO?

    The design looks fine to me though I would consider checking with someone from the LDO team to confirm that device's schematics. With the charger's design looks fine, one thing I would note is that the resistor naming conventions seem to be flipped (i.e. RUV1 connects to VRDRV and RUV2 connects to GND). This is fine and the values seem ok, but when referencing the datasheet it might be confusing as the datasheet uses the opposite convention:

    Best Regards,

    Juan Ospina

  • Hi Juan,

    We did see the same behavior on multiple boards, so we don't think it was a one-off soldering issue. Regardless, we don't think it is worth our time investigating with this design we now consider outdated.

    I will flip the resistor designators to match the datasheet.

    We want the battery to be able to charge to near 4.2 V. Does that mean we need to adjust the R_ov values?

    If the load is connected directly to the battery, it won't be cutoff if the battery voltage drops below VBAT_UV, correct?

    When doing the voltage divider calculations for the resistors, what should we consider VRDIV to be?

    We appreciate the support!

  • Hi Alex,

    If the load is connected directly to the battery, it won't be cutoff if the battery voltage drops below VBAT_UV, correct?

    That's right, typically this is included as a protection against significant battery discharge, but if you battery voltage at a lower voltage you can adjust VBAT_UV or connect directly to the battery.

    We want the battery to be able to charge to near 4.2 V. Does that mean we need to adjust the R_ov values?

    That's right. You can use the (3/2) * VRDRV * (1+ (ROV1/ROV2)) formula to calculate your R_ov required values. 

    what should we consider VRDIV to be?

    VRDIV should be equal to VBIAS on the EC table, typically 1.25V.

    Best Regards,

    Juan Ospina

  • Thanks. Related to my question in my email a few minutes ago about VRDIV, I found some documentation from the original designer of the power circuit. Please see attached. He has VBAT_UV as 2.998 V and VBAT_OV as 4.095 V. That is more in line with what we want, but disagrees with the values you gave in your 1:40pm MT email yesterday. Can you help us understand the discrepancy?

    Calcs_V2.pdf

  • Hi Alex,

    That's right. I was using a typical value of 1.2V which is what we use for the BQ25505 and BQ25570, which is slightly lower than the 1.25V used on this device. I believe the values shared in the PDF you shared are accurate. It looks like the values are selected with certain tolerances being accounted for. 4.095V would be the typical battery regulation voltage with the configured resistors.

    Best Regards,

    Juan Ospina