Dear all,
we are currently developing a full-bridge circuit using the PWM full-bridge controller: UCC3895. The issue consists of ringing artifacts observed at the drain-source voltage of the MOSFETs.
Figure 1: Drain-source voltage measurement at 30V input voltage for the full-bridge circuit. The Vds voltage at the MOSFETs has high-amplitude voltage spikes, which could potentially be due to the fast switching transitions from the controller's output signals.
We think that one of the potential reasons is the timing set by the output signals of the controller. The issue is that when using 4kOhm delay resistors, the PWM output signals from the controller do not comply with the full-bridge operation (first figure). Then, we changed the delay resistors to 1kOhm and it appears to work fine. However, the timing seems to tight and could be generating ringing artifacts.
Figure 2:Output signals for 4kOhm delay resistor: it does not follow correct full-bridge operation. All output signals are off for a 0.1us window.
Figure 3: Output signals for 1kOhm delay resistor: appears to follow correct full-bridge operation. However, the timing are probably too tight and produce artifacts in the circuit
We are open to suggestion what to study/tune regarding the delay resistor selection. Also, we were wondering if the duty cycle can be limited by the controller, which could potentially reduce the stress on the circuit.
Thanks in advanced.
