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LMZ12003: LMZ12003 Enable Pin Control Mechanism

AM
Prodigy 10 points
Part Number: LMZ12003

Hello, I am attempting to use the LMZ12003 for a current limiting application. I would like to know if there is a way I can prevent potential damage to an IO bank to an FPGA that is driving the enable pin, since this enable pin is pulled up to Vin. This Vin obviously exceeds the voltage that the IO pin is rated at. I want to be able to use this FPGA IO pin to basically enable/disable this regulator.

  • 0
    TI__Genius 10460 points

    Hi,

    I'm not very clear about your requirement. Do you want to control the EN pin by both VIN and IO? 

    Regards,

    Shipeng

  • 0 in reply to Shipeng Cheng
    Prodigy 10 points

    I believe I have figured out a solution. I wanted to control the enable output so that it gets pulled low and turns off the regulator when a defined logic state of 0 is being applied to it. And vice-versa for a logic state of 1. I decided to go with a buffer with an open-drain output to do this. Since the chip pulls EN up to VIN internally, I was concerned that the VIN I am applying would damage the IO bank of the FPGA I am driving it with since that VIN exceeds the maximum voltage that these IO are capable of handling.

  • 0 in reply to AM
    TI__Genius 10460 points

    Hi,

    An open-drain buffer is OK to do this. But I suggest to add two resistors as a divider to avoid noise causing wrong action. Thanks. 

    Regards,

    Shipeng