Other Parts Discussed in Thread: ALLIGATOR
Tool/software:
Hi TI-Team,
I have a question regarding the rise time Tr of the LMG1020 GaN driver. My setup: LMG1020 directly connected to an EPC2019 without any gate resistors in between. The layout is as compact as possible. The GaN is switching 6.5 V via a 10k resistor to zero when turned on (so the transistor is switching a pretty small load).
Unfortunately, the performance is not quite as good as I wish. According to the datasheet, the typical output rise time of the driver should be around 375 ps @ 100 pF load. The EPC2019 has an input capacitance (CISS) of typ. 254 pF and my scope+cable add another 20+60 pF load to the gate drivers output while measuring the signal.
In this setup, the measured rise time of the LMG1020 is 1.20 ns, so around 3.2 times slower, but its also driving a 3.3 times higher capacitive load as for which the rise time was specified in the datasheet.
No "rise time vs load" is provided in the datasheet, therefore I'd like to know if there's some linear correlation between those two values? Can you provide a "rise time vs load" graph for this driver? Is the rise time as I measure it plausible?
I'm referring to a question already asked in this forum, where somebody had a similar problem with an EPC2001C GaN FET, which has a significantly higher input capacitance compared to mine and tried to achieve rise times <1 ns. The thread seems to be solved, but a solution has been found in private and was not posted public.
I'm looking forward for your answer!
Lukas