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Original question:

LMG1020: How to improve rise time (Tr) if connected to a GaNFet (EPC2001C)

LMG1020: Rise time (Tr) higher than expected

Lukas Zeitler
Prodigy 20 points
Part Number: LMG1020
Other Parts Discussed in Thread: ALLIGATOR

Tool/software:

Hi TI-Team,

I have a question regarding the rise time Tr of the LMG1020 GaN driver. My setup: LMG1020 directly connected to an EPC2019 without any gate resistors in between. The layout is as compact as possible. The GaN is switching 6.5 V via a 10k resistor to zero when turned on (so the transistor is switching a pretty small load).

Unfortunately, the performance is not quite as good as I wish. According to the datasheet, the typical output rise time of the driver should be around 375 ps @ 100 pF load. The EPC2019 has an input capacitance (CISS) of typ. 254 pF and my scope+cable add another 20+60 pF load to the gate drivers output while measuring the signal.

In this setup, the measured rise time of the LMG1020 is 1.20 ns, so around 3.2 times slower, but its also driving a 3.3 times higher capacitive load as for which the rise time was specified in the datasheet.

No "rise time vs load" is provided in the datasheet, therefore I'd like to know if there's some linear correlation between those two values? Can you provide a "rise time vs load" graph for this driver? Is the rise time as I measure it plausible?

I'm referring to a question already asked in this forum, where somebody had a similar problem with an EPC2001C GaN FET, which has a significantly higher input capacitance compared to mine and tried to achieve rise times <1 ns. The thread seems to be solved, but a solution has been found in private and was not posted public.

I'm looking forward for your answer!

Lukas

  • 0
    Prodigy 20 points

    I want to add some additional context: the eval module LMG1020EVM-006 uses the same components like in my project, but is advertised with "210 ps typical rise/fall time".

    The fall time (80-20) of my GaN switching the above mentioned 6.5 V to zero via a 10k resistor is btw 900 ps, so significantly longer.

  • 0 in reply to Lukas Zeitler
    TI__Mastermind 21785 points

    Hello Lucas,

    Our expert on this device is out of the office today and will be back next week. He may need to address the detail questions. But the driver rise and fall times will be dependent on the capacitive load, as one variable. So the increased effective capacitance of the GaN Fets will have an effect. With these very short rise and fall times the parasitic inductance in the gate drive loop will be very critical and will affect the performance.

    Regards,

  • 0
    TI__Expert 6325 points

    Hi Lukas,

    Apologies for the delay. Confirming what Richard said, it is true that the gate driver's rise and fall time is affected by the capacitive load (larger the load, longer the rise/fall time). Other factors like layout and parasitics can affect rise and fall time as well.

    Unfortunately, we do not have data for rise/fall time vs. load for the LMG1020. You could potentially lower the rise/fall time by making sure that the layout traces are short as possible (input and output) and that the VDD bypass capacitor is between 0.1uF to 1uF, small in size (0201), and as close as possible to the driver. You should also use oscilloscope probes with a “pigtail” spring ground clip instead of the standard alligator clip to reduce parasitics as much as possible.

    The LMG1020EVM product page has not been updated to reflect the revised user guide, which has 400ns. That 400ns also applies to the gate driver IC, and not the EVM as a whole.

    Thanks,
    Rubas

  • 0 in reply to Rubas Khalid
    Prodigy 20 points

    Hi Rubas,

    thanks for your reply! In my opinion, my layout is already optimized as much as possible. However, I'm using a 0.1uF (0201) in parallel with a 10uF (0402) as VDD bypass capacitors, obviously as close to the IC as possible.

    Why do you suggest to keep the bypass capacitors value within the given limits? Personally, I don't really understand how a bypass capacitor bigger than the suggested values can be critical for the rise/fall time at the output of the gate driver? Could you please elaborate?

    Best regards,

    Lukas

  • 0 in reply to Lukas Zeitler
    TI__Expert 6325 points

    Hi Lukas,

    I apologize, I meant to say 0.1uF to 10uF. These are the typical capacitor values for VDD bypass, and while going bigger won't necessarily hurt the system, going too big could potentially slow VDD charge. I should've been more clear on that part though, because the main point of mentioning the bypass capacitors was to make sure the layout is done efficiently, which is important for a GaN application. If your layout is already optimized, then try to use the pigtail method when probing the signals to reduce any potential parastics when measuring the signals.

    Thanks,
    Rubas

  • 0 in reply to Rubas Khalid
    Prodigy 20 points

    Hi Rubas,

    thanks for your reply! So basically the essence is that my GaN FET with its capacitive load is the limiting factor. In order to achieve a faster switching edge, I'd have to reconsider this part.

    Thanks for your help!

    Lukas

  • 0 in reply to Lukas Zeitler
    TI__Expert 6325 points

    No problem! Yes, it's the capacitive load that mainly affects the rise and fall time.

    Thanks,
    Rubas