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TPS54202: request for layout review

Part Number: TPS54202
Other Parts Discussed in Thread: LMR51420

Tool/software:

Hello TI Engineers,

I would like your assistance in reviewing a 4 Layer PCB Layout of a 5V Regulator Design for the TPS54202 Buck IC. Below is a screen shot of the Schematic and Layout; One version of the layout only shows the top (red) and bottom layer (blue) the other shows the two inner layers which are Ground Planes. The design was made with web bench design. The Layout was a combination of the layout generated by the web bench and the layout suggestion on the datasheet. Where I used the space between the input capacitor to route the SW Pin to the Inductor but I did not need to via down to the bottom layer to do the routing. The output capacitors are also connected to the ground plane where the ground pin of the IC is also connected to. 

Schematic

Layout

Webbench vs Datasheet Layout

Thanks,

Deniel

  • Hi Deniel,

    Thanks for reaching out! Bella will give you response by end of this week. Thanks!

    BRs

    Lucia

  • Hi Deniel

    Schematic:

    Add a 0.1uF Cin and place this Cin as close as possible to the VIN and GND pin.

    Inductor: Recommend select L with Isat larger than the device current limit, (ILIM_HS=3.2A as you can see in the EC table in the datasheet of TPS54202)

     

    Layout:

    The SW node is noisy and please keep the copper plane smaller. It's better to keep SW trace short and wide. You can refer to the Figure 9-10 Layout example in LMR51420 datasheet, which is pin2pin with TPS54202.

    RL8 should be placed both close to FB pin and the GND pin. The RL8 to GND trace is long.

    The CL2 should be placed close to BST and SW.

    Thanks and best regards.

  • Hello Gui,

    Thanks for the initial review of the schematic and layout. I have below the updated schematic and layout. Let me know if the adjustments are good.

    Schematic

    I have added an additional 100nFcapacitor CL9 in the schematic. The Inductor in the schematic is based on the Web Bench design we have. Our Max output current of the 5V regulator is only 0.5A. This is the reason why our inductor is 2A rated current and 2.05A Saturation current. Do we still need to the inductor with a saturation current higher than the device current limit? 

    Updated Layout

    I followed the LMR51420 Datasheet Layout Guide in Figure 9-10 and the LMR51420 EVM Layout

    1. CL9 and CL6 input capacitors are closer the Input Pin

    2. Is the VIN width sufficient enough. The width of VIN affected the SW Pin polygon shape

    3. RL8 is now closer to both GND pin via the Ground Plane and the FB pin

    4. BST Capacitor, CL2, is now at the bottom layer to make the routing shorter. Should I move it even closer to the start of the SW pin copper pour since it is already in the bottom layer? How close can I place the via going down from the SW pin copper pour to the BST Cap?

    Do you have additional comments on the layout?

    Top Layer with Components

    Bottom Layer

    Regards,

    Deniel

  • Hi Deniel

    The layout looks good to me. Just that you can adjust the SW plane angle since this will not impact the current path and will leave more place for the GND plane.  For the BOOT capacitor, I think it's good as it is .the VIN width should also be sufficient.

    Under specific operate conditions like the output short-circuited , the iL can be high and hit the ILIM, if Isat is small, the inductor will saturate and there might be some risk. This is why we normally recommend selecting inductor with Isat>ILIM. You can check the system operation and the saturate curve of the inductor and decide.

    Thanks and best regards.

  • Hello Gui,

    Thanks for the review for the updated layout. We will change the SW pin copper plane similar to your suggestion and expand the top layer GND copper plane. We will also change the inductor to coil craft XGL6060-822 which has higher Saturation current compared to  ILIM of the buck IC.

    Thanks,

    Deniel